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Design of FPGA Interconnect for Multilevel Metalization

Article by André DeHon and Raphael Rubin published in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 12, Number 10, Pages 1038--1050, October 2004.

How does multilevel metallization impact the design of FPGA interconnect? The availability of a growing number of metal layers presents the opportunity to use wiring in the third-dimension to reduce area and switch requirements. Unfortunately, traditional FPGA wiring schemes are not designed to exploit these additional metal layers. We introduce an alternate topology, based on Leighton's Mesh-of-Trees, which carefully exploits hierarchy to allow additional metal layers to support arbitrary device scaling. When wiring layers grow sufficiently fast with aggregate network size (N), our network requires only O(N) area; this is in stark contrast to traditional, Manhattan FPGA routing schemes where switching requirements alone grow superlinearly in N. In practice, we show that, even for the admittedly small designs in the Toronto ``FPGA Place and Route Challenge,'' arity-4 Mesh-of-Trees networks require 26% fewer switches than the standard, Manhattan FPGA routing scheme.