Nanowire-Based Sublithographic Programmable Logic Arrays (FPGA2004)


Nanowire-Based Sublithographic Programmable Logic Arrays

Article by André DeHon and Michael J. Wilson published in Proceedings of the International Symposium on Field-Programmable Gate Arrays (FPGA2004, February 22--24, 2004), pp. 123--132.

How can Programmable Logic Arrays (PLAs) be built without relying on lithography to pattern their smallest features? In this paper, we detail designs which exploit emerging, bottom-up material synthesis techniques to build PLAs using molecular-scale nanowires. Our new designs accommodate technologies where the only post-fabrication programmable element is a non-restoring diode. We introduce stochastic techniques which allow us to restore the diode logic at the nanoscale so that it can be cascaded and interconnected for general logic evaluation. Under conservative assumptions using 10nm nanowires and 90nm lithographic support, we project yielded logic density around 500,000nm²/or term for a 60 or-term array; a complete 60-term, two-level PLA is roughly the same size as a single 4-LUT logic block in 22nm lithography. Each or term is comparable in area to a 4-transistor hardwired gate at 22nm. Mapping sample datapaths and conventional programmable logic benchmarks, we estimate that each 60-or-term PLA plane will provide equivalent logic to 5--10 4-input LUTs.

This paper was recognized in the FPGA20 collection of the most significant papers during the first 20 years of the conference. See retrospective endorsement.

Paper

Author's extended PDF version nanopla_fpga2004_extended.pdf [930KB]
(contains appendicies not included in FPGA'04 proceedings copy)

follow up paper in FPGA'05 Design of Programmable Interconnect for Sublithographic Programmable Logic Arrays

Nanowire-Based Sublithographic Programmable Logic Arrays

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