Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices
We present a novel 3D crossbar for future Network-on-a-Chip implementations. We introduce a routing algorithm for the 3D crossbar circuit and detail two specific 3D crossbar topologies. We evaluate the defect tolerance of the 3D crossbar and quantify the number of extra layers required to support arbitrary permutations as a function of the defect rate. Further, we estimate the circuit performance and advantages of the 3D crossbar circuit based on post-silicon devices.
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