Implementation of Computation Group (CALTECH, Dept. of CS)

Programmable System-on-a-Chip Architecture

Heterogeneous PSOC
with uP, FPGA, and Memory Heterogeneous PSOC
with uP, FPGA, FPU, and Memory

With the silicon capacity available today, ISA-based, general-purpose processors are hitting a point of diminishing returns---where it is hard for them to fully exploit the available silicon. At the same time, we're seeing evidence that spatial architectures (e.g. FPGAs) can provide higher performance per unit area than processors for many regular applications while still providing a programmable substrate. In general, today's IC's are large enough to easily contain a rich collection of uP's, spatial array logic, memory, and specialized processing units. This raises several important questions: How do we navigate this new design space enabled by modern silicon capacity? How do we combine these diverse components in a systematic way? What abstraction(s) should replace the ISA, giving the user and compiler a robust fixed point, while allowing implementations to scale and exploit the inevitable and regular increase in silicon capacity?
For a look at the role of spatial architectures, see The Density Advantage of Configurable Computing. For our initial ideas on a compute model and abstractions for Programmable System-on-a-Chip designs, see the SCORE tutorial.


Heterogeneous PSOC with uP, FPGA, and Memory	Heterogeneous PSOC with uP, FPGA, FPU, and Memory
With the silicon capacity available today, ISA-based, general-purpose processors are hitting a point of diminishing returns---where it is hard for them to fully exploit the available silicon. At the same time, we're seeing evidence that spatial architectures (e.g. FPGAs) can provide higher performance per unit area than processors for many regular applications while still providing a programmable substrate. In general, today's IC's are large enough to easily contain a rich collection of uP's, spatial array logic, memory, and specialized processing units. This raises several important questions: How do we navigate this new design space enabled by modern silicon capacity? How do we combine these diverse components in a systematic way? What abstraction(s) should replace the ISA, giving the user and compiler a robust fixed point, while allowing implementations to scale and exploit the inevitable and regular increase in silicon capacity? For a look at the role of spatial architectures, see The Density Advantage of Configurable Computing. For our initial ideas on a compute model and abstractions for Programmable System-on-a-Chip designs, see the SCORE tutorial.