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References

ABI +95

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ACC +96

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ADD90

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AFM +89

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AKY +96

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AL94

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Alg90

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Alt94

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ANAB +92

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ANH +88

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AOT +94

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ASO +90

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Atm94

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BAB +95

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BBB +95

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BCK93

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BDN84

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BFRV92

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Bha93

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BTA93

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CC86

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CCS +91

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CD96

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CDd +95

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CDF +95

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CDH +88

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CKC +89

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CLRA90

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FHT +92

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FOS +89

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FOW +86

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FPH +90

Stephen Flannagan, Perry Pelley, Norman Herr, Bruce Engles, Taisheng Feng, Scott Nogle, John Eagan, Robert Dunnigan, Lawrence Day, and Roger Kung. 8-ns CMOS 64K4 and 256K1 SRAM's. IEEE Journal of Solid-State Circuits, 25(5):1049-1054, October 1990.

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FRV +86

Stephen Flannagan, Paul Reed, Peter Voss, Scott Nogle, Lawrence Day, David Sheng, John Barnes, and Roger Kung. Two 13-ns 64K CMOS SRAM's with Very Low Active Power and Improved Asynchronous Circuit Techniques. IEEE Journal of Solid-State Circuits, 21(5):692-703, October 1986.

FSO +86

Syuso Fujii, Shozo Saito, Yoshio Okada, Masayuki Sato, Shizuo Sawada, Satoshi Shinozaki, Kenji Natori, and Osamu Ozawa. A 50-A Standby 1M1/256K4 CMOS DRAM with High-Speed Sense Amplifier. IEEE Journal of Solid-State Circuits, 21(5):643-647, October 1986.

Gam81

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GBB +96

Paul Gronowski, Peter Bannon, Michael Bertone, Randel Blake-Campos, Gregory Bouchard, William Bowhill, David Carlson, Ruben Castelino, Dale Donchin, Richard Fromm, Mary Gowan, Anil Jain, Bruce Loughlin, Shekhar Mehta, Jeanne Meyer, Robert Mueller, Andy Olesin, Tung Pham, Ronald Preston, and Paul Robinfeld. A 433MHz 64b Quad-Issue RISC Microprocessor. In 1996 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pages 222-223. IEEE, February 1996.

GGA +85

Abbas El Gamal, David Gluss, Peng-Huat Ang, Jonathan Greene, and Justin Reyneri. A CMOS 32b Wallace Tree Multiplier-Accumulator. In 1985 IEEE International Solid-State Circuits Conference, Digst of Technical Papers, pages 194-195. IEEE, February 1985.

GHH +96

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GHK +91

Maya Gokhale, William Holmes, Andrew Kopser, Sara Lucas, Ronald Minnich, Douglas Sweely, and Daniel Lopresti. Building and Using a Highly Programmable Logic Array. IEEE Computer, 24(1):81-89, January 1991.

GHS +87

Will Gubbels, Cornelis Hartgring, Roelof Salters, Jos Lammerts, Michael Tooher, Patrick Hens, Joseph Bastiaens, Jan Dijk, and Marc Sprokel. A 40-ns/100-pF Low-Power Full-CMOS 256K (32K8) SRAM. IEEE Journal of Solid-State Circuits, 22(5):741 ff., October 1987.

GK89

John Gray and Tom Kean. Configurable Hardware: A New Paradigm for Computation. In Charles Seitz, editor, Advanced Research in VLSI: proceedings of teh Decennial Caltech Conference on VLSI, pages 279-295, March 1989.

GM93

Maya Gokhale and Ron Minnich. FPGA Computing in a Data Parallel C. In Duncan A. Buell and Kenneth L. Pocek, editors, Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, pages 94-101, Los Alamitos, California, April 1993. IEEE Computer Society, IEEE Computer Society Press.

GN94

Greg Goslin and Bruce Newgard. 16-TAP, 8-Bit FIR Filter Applications Guide. Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, November 1994. http://www.xilinx.com/appnotes/fir_filt.pdf.

GNAB93

Jeffrey Gray, Andrew Naylor, Arthur Abnous, and Nader Bagherzadeh. VIPER: A VLIW Integer Microprocessor. IEEE Journal of Solid-State Circuits, 28(12):1377-1382, December 1993.

GNC +90

Carla Golla, Fulvio Nava, Franco Cavallotti, Alessandro Cremonesi, and Giulio Casagrande. 30-MSamples/s Programmable Filter Processor. IEEE Journal of Solid-State Circuits, 25(6):1502-1509, December 1990.

GOI95

Eric Gayles, Robert Owens, and Mary Jane Irwin. The MGAP-2: A Micro-Grained Massively Parallel Array Processor. In Eith Annual IEEE International ASIC Conference and Exhibit, pages 333-337, April 1995.

GOK +92

Hiroyuki Goto, Hiroaki Ohkubo, Kenji Kondou, Masayoshi Ohkawa, Hitoshi Mitani, Shinichi Horiba, Masakazu Soeda, Fumihiko Hayashi, Yutaro Hachiya, Toshiyuki Shimizu, Manabu Ando, and Zensuke Matsuda. A 3.3-V 12-ns 16-Mb SRAM. IEEE Journal of Solid-State Circuits, 27(11):1490-1496, November 1992.

Gol87

Alex Goldberger. A High Performance, Easy to Program DSP for General Purpose Applications. In Mini/Micro Northeast Conference Record, pages 27/3 1-10, April 1987.

Gra94

Jan Gray. homebuilt processors using FPGAs (long). December 11, 1994 posting to comp.arch.fpga. Author may be reached at jsgray@ix.netcom.com, December 1994.

Gra96

Jan Gray. j32 FPGA Processor. Personal communications jsgray@ix.netcom.com, February 1996.

Gro87

Robert Grondalski. A VLSI Chip Set for Massively Parallel Architecture. In IEEE International Solid-State Circuits Conference, pages 198-199, 1987.

GSNS92

Gensuke Goto, Tomio Sato, Masao Nakajima, and Takao Sukemura. A 5454-b Regularly Structured Tree Multiplier. IEEE Journal of Solid-State Circuits, 27(9):1229-1236, July 1992.

HAH +92

Hideto Hidaka, Kazutami Arimoto, Kazutoshi Hirayama, Masanori Hayashikoshi, Mikio Asakura, Masaki Tsukude, Tsukasa Oishi, Shinji Kawai, Katsuhiro Suma, Yasuhiro Konishi, Koji Tanaka, Wataru Wakamiya, Yoshikazu Ohno, and Kazuyasu Fujishima. A 34-ns 16-Mb DRAM with Controllable Voltage Down-Converter. IEEE Journal of Solid-State Circuits, 27(7):1020 ff., July 1992.

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Chuck Hastings. When is a Memory Not a Memory. In Proceedings of the Electro/87 Mini/Micro Northeast, pages 1132, 4/5/1-18, 1987.

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David Hawley. Advanced PLD Architectures. In Will Moore and Wayne Luk, editors, FPGAs, pages 11-23. Abingdon EE&CS Books, 15 Harcourt Way, Abingdon, OX14 1NV, UK, 1991.

HBD94

Robert Heaton, Donald Blevins, and Edward Davis. A Bit-Serial VLSI Array Processing Chip for Image Procesing. IEEE Journal of Solid-State Circuits, 25(2):364-368, April 1994.

HDJ +88

Hung-Cheng Hsieh, Khue Duong, Jason Y. Ja, Roy Kanazawa, Luan T. Ngo, Liane G. Tinkey, Ross H. Freeman, and William S. Carter. A 9000-Gate User-Programmable Gate Array. In IEEE 1988 Custom Integrated Circuits Conference, pages 15.3.1-7. IEEE, May 1988.

HFML85

Dennis A. Henlin, Michael T. Fertsch, Moshe Mazin, and Edard T. Lewis. A 1616 Bit Pipelined Multiplier Macrocell. IEEE Journal of Solid-State Circuits, 20(2):542-547, April 1985.

HHC +87

Mark Horowitz, John Hennessy, Paul Chow, Glenn Gulak, John Acken, Anant Agarwal, Chorng-Yeung Chu, Scott McFarling, Steven Przybylski, Steven Richardson, Arturo Salz, Richard Simoni, Don Stark, Peter Steenkiste, Steven Tjiang, and Malcom Wing. A 32b Microprocessor with On-Chip 2K byte Instruction Cache. In 1987 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pages 30-31. IEEE, February 1987.

HKKM96

Makoto Hanawa, Kenji Kaneko, Tatsuya Kawashimo, and Hiroshi Maruyama. A 4.3 ns 0.3m CMOS 5454 Multiplier Using Precharged Pass-Transistor Logic. In 1996 IEEE International Solid-State Circuits Conference, Digst of Technical Papers, pages 364-365. IEEE, February 1996.

HKM +90

Toshihiko Hirose, Hirotada Kuriyama, Shuji Murakami, Kojiro Yuzuriha, Takao Mukai, Kazuhito Tsutsumi, Yasumasa, Nishimura, Yoshio Kohno, and Kenji Anami. A 20-ns 4-Mb CMOS SRAM with Hierarchical Word Decoding Architecture. IEEE Journal of Solid-State Circuits, 25(5):1068-1074, October 1990.

HOW +86

Fumio Horiguchi, Mitsugi Ogura, Shigeyoshi Watanabe, Koji Sakui, Naokazu Miyawaki, Yasuo Itoh, Kei Kurosawa, Fujio Masuoka, and Hisakazu Iizuka. A High-Performance 1-Mbit Dynamic RAM with a Folded Capacitor Cell. IEEE Journal of Solid-State Circuits, 21(6):1076-1082, December 1986.

HP90

John Hennessey and David Patterson. Computer Architecture a Quantitative Approach. Morgan Kaufmann Publishers, Inc., 1990.

HS84

Kye S. Hedlund and Lawrence Snyder. Systolic Architectures -- A Wafer Scale Approach. In Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers, pages 604-610. IEEE, IEEE Computer Society Press, October 1984.

HT95

Hannes Hassler and Naofumi Takagi. Function Evaluation by Table Look-up and Addition. In Proceedings of the 12th Symposium on Computer Arithmetic, pages 10-16, July 1995.

ID95

Tsuyoshi Isshiki and Wayne Wei-Ming Dai. High-Level Bit-Serial Datapath Synthesis for Multi-FPGA Systems. In Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pages 167-173. ACM, February 1995.

IIF +95

Hiroyuki Igura, Masanori Izumikawa, Koichiro Furuta, Tohru Mogami, Tadahiko Horiuchi, and Masakazu Yamashina. 100MHz, 0.55mm, 2mW, 16-b Stacked-CMOS Multiplier-Accumulator. In Proceedings of the IEEE 1995 Custom Integrated Circuits Conference, pages 597-600. IEEE, May 1995.

IKM +94

Koichiro Ishibashi, Kunihiro Komiyaji, Sadayuki Morita, Toshiro Aoto, Shuji Ikeda, Kyoichiro Asayama, Atsuyosi Koike, Toshiaki Yamanaka, Naotaka Hashimoto, Haruhito Iida, Fumio Kojima, Koichi Motohashi, and Katsuro Sasaki. A 12.5-ns 16-Mb CMOS SRAM with Common-Centroid-Geometry-Layout Sense Amplifiers. IEEE Journal of Solid-State Circuits, 29(4):411 ff., April 1994.

IYK +88

Michihiro Inoue, Toshio Yamada, Hisakazu Kotani, Hiroyuki Yamauchi, Atsushi Fujiwara, Junko Matsushima, Hironori Akamatsu, Masanori Fukumoto, Masafumi Kubota, Ichiro Nakao, Nobuo Aoi, Genshu Fuse, Shin-Ichi Ogawa, Shinji Odanaka, Atsushi Ueno, and Hiroshi Yamamoto. A 16-Mbit DRAM with a Relaxed Sense-Amplifier-Pitch Open-Bit Line Architecture. IEEE Journal of Solid-State Circuits, 23(5):1104-1112, October 1988.

JF72

J. Robert Jump and Dennis R. Fritsche. Microprogrammed Arrays. IEEE Transactions on Computers, 21(9):974-984, September 1972.

JL95

David Jones and David Lewis. A Time-Multiplexed FPGA Architecture for Logic Emulation. In Proceedings of the IEEE 1995 Custom Integrated Circuits Conference, pages 495-498. IEEE, May 1995.

JOSV95

Chris Jones, John Oswald, Brian Schoner, and John Villasenor. Issues in Wireless Video Coding using Run-time-reconfigurable FPGAs. In Peter Athanas and Ken Pocek, editors, Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, Los Alamitos, California, April 1995. IEEE Computer Society, IEEE Computer Society Press.

KAI +86

Yoshifumi Kobayashi, Kazutami Arimoto, Yuto Ikeda, Masahiro Hatanaka, Koichiro Mashiko, Michihiro Yamad, and Takao Nakano. A High-Speed 64K4 CMOS CRAM Using On-Chip Self-Timing Techniques. IEEE Journal of Solid-State Circuits, 21(5):655-661, October 1986.

KCE +85

Howard L. Kaltzer, Pierre D. Coppens, Wayne F. Ellis, John A. Fifield, Daryl J. Kokoszka, Terry L. Leasure, Christopher P. Miller, Quan Nguyen, Ronald E. Papritz, Charles S. Patton, J. Michael Poplawski, Jr., Steven W. Tomashot, and Willem B. Van Der Hoeven. An Experimental 80-ns 1-Mbit DRAM with Fast Page Operation. IEEE Journal of Solid-State Circuits, 20(5), October 1985.

KDK +90

Yasuhiro Konishi, Katsumi Dosaka, Takahiro Komatsu, Yoshinori Inoue, Masaki Kumanoya, Youichi Tobita, Hideki Genjyo, Masao Nagatomo, and Tsutomu Yoshihara. A 38-ns 4-Mb DRAM with A Battery-Backup (BBU) Mode. IEEE Journal of Solid-State Circuits, 25(5):1112-1117, October 1990.

KDK +92

Toshiaki Kirihata, Sang Dhong, Koji Kitamura, Toshio Sunaga, Yasunao Katayama, Roy Scheuerlein, Akashi Satoh, Yoshinori Sakaue, Kentaroh Tobimatsu, Koji Hosokawa, Takaki Saitoh, Takefumi Yoshikawa, Hideki Hashimoto, and Michiya Kazusawa. A 14-ns 4-Mb DRAM with 300-mW Active Power. IEEE Journal of Solid-State Circuits, 27(9):1222 ff., September 1992.

KDS +96

Shinichi Kozu, Masayuki Daito, Yukinori Sugiyama, Hiroaki Suzuki, Hiroshi Morita, Masahiro Nomura, Kouhei Nadehara, Souichiro Ishibuchi, Masako Tokuda, Yoshihisa Inoue, Takashi Nakayama, Hisao Harigai, and Yoichi Yano. A 100MHz, 0.4W Processor with 200MHz Multiply-Adder, using Pulse-Register Technique. In 1996 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pages 140-141. IEEE, February 1996.

Kea89

Tom Kean. Configurable Logic: A Dynamically Programmable Cellular Architecture and its VLSI Implementation. PhD thesis, University of Edinburgh, January 1989.

KEK +85

Yasuo Kobayashi, Hirotsugo Eguchi, Osamu Kudoh, Toshio Hara, Hideyuki Ooka, Isao Sasaki, Manabu Andoh, and Masato Tameda. A 10-W Standby Power 256K CMOS SRAM. IEEE Journal of Solid-State Circuits, 20(5):935-940, October 1985.

KFM +85

Masaki Kumanoya, Kazuyasu Fujishima, Hideshi Miyatake, Yasumasa, Nishimura, Kazunori Saito, Takayuki, Matsukawa, Tsutomu Yoshihara, and Takao Nakano. A Reliable 1-Mbit DRAM with Multi-Bit-Test Mode. IEEE Journal of Solid-State Circuits, 20(5), October 1985.

KFO84

Robert A. Kertis, Kerlly J. Fitzpatrick, and Kul B. Ohri. A 60 ns 256K1 Bit DRAM Using Technology and Double-Level Metal Interconnection. IEEE Journal of Solid-State Circuits, 19(5):585-590, October 1984.

KHANW94

Alan Y. Kwentus, Hing-Tsun Hung, and Jr. Alan N. Wilson. An Architecture for High-Performance/Small-Area Multipliers for Use in Digital Filtering Applications. IEEE Journal of Solid-State Circuits, 29(2):117-121, February 1994.

KHK +93

Goro Kitsukawa, Masashi Horiguchi, Yoshiki Kawajiri, Takayuki Kawahara, Takesada Akiba, Yasushi Kawase, Toshikazu Tachibana, Takeshi Sakai, Masakazu Aoki, Syoji Shukuri, Kazuhiko Sagara, Ryo Nagai, Yuzuru Ohji, Norio Hasegawa, Natsuki Yokoyama, Teruaki Kisu, Hisaomi Yamashita, Tokuo Kure, and Takashi Nishida. 256-Mb DRAM Circuit Technologies for File Applications. IEEE Journal of Solid-State Circuits, 28(11):1105-1112, November 1993.

KHN +96

Masuyoshi Kurokawa, Akihiko Hashiguchi, Ken'ichiro Nakamura, Hiroshi Okuda, Koji Aoyama, Takao Yamazaki, Mitsuharu Ohki, Mitsuo Soneda, Katsunori Seno, Ichiro Kumata, Masatoshi Aikawa, Hirokazu Hanaki, and Seiichiro Iwase. 5.4GOPS Linear Array Architecture DPS for Video-Format Conversion. In 1996 IEEE International Solid-State Circuits Conference, Digst of Technical Papers, pages 254-255. IEEE, February 1996.

KIK +86

Shinpei Kayano, Katsuki Ichinose, Yoshio Kohno, Hirofumi Shinohara, Kenji Anami, Shuji Murakami, Tomohisa Wada, Yuji Kawai, and Yoichi Akasaka. 25-ns 256K1/64K4 CMOS SRAM's. IEEE Journal of Solid-State Circuits, 21(5):686-691, October 1986.

KK79

Steven I. Kartashev and Svetlana P. Kartashev. A multicomputer Systems with Dynamic Architecture. IEEE Transactions on Computers, 28(10):704-720, October 1979.

KKHY88

Shoji Kawahito, Michitaka Kameyama, Tatsuo Higuchi, and Haruyaso Yamada. A 32 32-bit Multiplier Using Multiple-Valued MOS Current-Mode Circuits. IEEE Journal of Solid-State Circuits, 23(1):124-132, February 1988.

KNK +87

Kenji Kaneko, Tetsuya Nakagawa, Atsushi Kiuchi, Yoshimune Hagiwara, Hirotada Ueda, and Hitoshi Matsushima. A 50ns DSP with Parallel Processing Architecture. In 1987 IEEE International Solid-State Circuits Conference, Digst of Technical Papers, pages 158-159. IEEE, February 1987.

Knu71

Donal E. Knuth. Empirical Study of FORTRAN Programs. Software Practice and Experience, 1(1):105-133, 1971.

Knu81

Donal E. Knuth. The Art of Computer Programming, volume 2. Addison Wesley, Reading, Massachusetts, 2nd edition, 1981.

KOT +96

Hideyuki Kabuo, Minoru Okamoto, Isao Tanaka, Hiroyuki Yasoshima, Shinichi Marui, Masayuki Yamasaki, Toshio Sugimura, Katsuhiko Ueda, Toshihiro Ishikawa, Hidetoshi Suzuki, and Ryuichi Asahi. An 80-MOPS-Peak High-Speed Low-Power Consumption 16-b Digital Signal Processor. IEEE Journal of Solid-State Circuits, 31(4):494-503, April 1996.

KSB +90

Howard Kalter, Charles Stapper, John Barth, Jr., John DiLorenzo, Charles Drake, John Fifield, Gordon Kelly, Jr., Soctt Lewis, Willem Van Der Hoeven, and James Yankosky. A 50-ns 16-Mb DRAM with a 10-ns Data Rate and On-Chip ECC. IEEE Journal of Solid-State Circuits, 25(5):1118 ff., October 1990.

KSE +87

Katsutaka Kimura, Katsuhiro Shimohigashi, Jun Etoh, Masamichi Ishihara, Kazuyuki Miyazawa, Shinji Shimizu, Yoshio Sakai, and Kunihiro Yagi. A 65-ns 4-Mbit CMOS DRAM with a Twisted Driveline Sense Amplifier. IEEE Journal of Solid-State Circuits, 22(5):651-656, October 1987.

KSY +84

Hiroshi Kawamoto, Takashi Shinoda, Yasunori Yamaguchi, Shinji Shimizu, Kanji Ohishi, Nobuyoshi Tnimura, and Tokumasa Yasui. A 288K CMOS Psedostatic RAM. IEEE Journal of Solid-State Circuits, 19(5):619-623, October 1984.

KT93

Won Kim and Russ Tuck. MasPar MP-2 PE Chip: A Totally Cool Hot Chip. In Proceedings of Hot Chips V, MasPar Computer Corporation, 749 North Mary Avenue, Sunnyvale, CA 94086, August 1993.

KTO +87

Takaaki Komatsu, Hitoshi Taniguchi, Nobumichi Okazaki, Toshiyuki Nishihara, Shigeki Kayama, Naoya Hoshi, Jun-Ichi Aoyama, and Takashi Shimada. A 35-ns 128K8 CMOS SRAM. IEEE Journal of Solid-State Circuits, 22(5):721-726, October 1987.

Kun82

H. T. Kung. Why Systolic Architectures? IEEE Computer, 15(1):37-46, January 1982.

KWA +88

Yoshio Kohno, Tomohisa Wada, Kenji Anami, Yuji Kawai, Kojiro Yuzuriha, Takayuki Matsukawa, and Shimpei Kayano. A 14-ns 1-Mbit CMOS SRAM with Variable Bit Organization. IEEE Journal of Solid-State Circuits, 23(5):1060-1066, October 1988.

LBK +89

Nicky Lu, Gary Bronner, Koji Kitamur, Roy Scheuerlein, Walter Henkels, Sang Dhong, Yasunao Katayama, Toshiaki Kirihata, Hideto Niijima, Robert Franch, Wei Hwang, Motoo Nishiwaki, Frank Pesavento, T. V. Rajeevakumar, Yoshinori Sakaue, Yasusuke Suzuki, Yasunori Iguchi, and Eiji Yano. A 22-ns 1-Mbit CMOS High-Speed DRAM with Address Multiplexing. IEEE Journal of Solid-State Circuits, 24(5):1198 ff., October 1989.

LC95

Jianmin Li and Chung-Kuan Cheng. Routability Improvement Using Dynamic Interconnect Architecture. In Peter Athanas and Ken Pocek, editors, Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, pages 61-67, Los Alamitos, California, April 1995. IEEE Computer Society, IEEE Computer Society Press.

LCwH +88

Nicky Lu, Hu Chao, wei Hwang, Walter Henkels, T. V. Rajeevakumar, Hussein Hanafi, Lewis Terman, and Robert Franch. A 20-ns 128-kbit4 High-Speed DRAM with 330-Mbit/s Data Rate. IEEE Journal of Solid-State Circuits, 23(5):1140 ff., October 1988.

LE94

Marianne E. Louie and Milos D. Ercegovac. A Variable Precision Multiplier for Field Programmable Gate Arrays. In Second International ACM/SIGDA Workshop on Field-Programmable Gate Arrays. ACM, February 1994. proceedings not available outside of the workshop.

LE96

Per Larsson-Edefors. A 965-Mb/s 1.o-m Standard CMOS Twin-Pipe Serial/Parallel Multiplier. IEEE Journal of Solid-State Circuits, 31(2):230-239, February 1996.

Lei79

Charles Leiserson. Systolic Priority Queues. CMU-CS-TR 115, Carnegie-Mellon University, Pittsbugh, Pennsylvania 15213, April 1979.

Lev77

Lance Leventhal. Cut Your Processor's Computation Time. Electronic Design, 25(17):82-88, August 16 1977.

LGC84

Claude P. Lerouge, Pierre Girard, and Joel S. Colardelle. A Fast 16 Bit Parallel Multiplier. IEEE Journal of Solid-State Circuits, 19(3):338-342, June 1984.

LGS87

Josephy Y. Lee, Hugh L. Garvin, and Charles W. Slayman. A High-Speed High-Density Silicon 88-bit Parallel Multiplier. IEEE Journal of Solid-State Circuits, 22(1):35-40, February 1987.

LLNK96

Jon Lotz, Gregg Lesartre, Samuel Naffziger, and Don Kipp. A Quad-Issue Out-of-Order RISC CPU. In 1996 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pages 210-211. IEEE, February 1996.

LR71

B. S. Landman and R. L. Russo. On Pin Versus Block Relationship for Partitions of Logic Circuits. IEEE Transactions on Computers, 20:1469-1479, 1971.

LRSS84

Chris Lutz, Steve Rabin, Chuck Seitz, and Don Speck. Design of the MOSAIC Element. In Paul Penfield, Jr., editor, Proceedings, Conference on Advanced Research in VLSI, pages 1-10, Cambdrige, MA, January 1984.

LS90

Junien Labrousse and Gerrit Slavenburg. A 50MHz Microprocessor with a Very Long Instruction Word Architecture. In 1990 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pages 44-45. IEEE, February 1990.

LS92

Joe Laskowski and Henry Samueli. A 150-MHz 43-Tap Half-Band FIR Digital Filter in 1.2-m CMOS Generated by Silicon Compiler. In Proceedings of the IEEE 1992 Custom Integrated Circuits Conference, pages 11.4.1-11.4.4. IEEE, May 1992.

LS93

Fang Lu and Henry Samueli. A 200-MHz CMOS Pipelined Multiplier-Accumulator Using a Quasi-Domino Dynamic Full-Adder Cell Design. IEEE Journal of Solid-State Circuits, 28(2):123-132, February 1993.

Mal94

Lisa Maliniak. Hardware Emulation Draws Speed From Innovative 3D Parallel Processing Based on Custom ICs. Electronic Design, pages 38-41, May 30 1994.

MD96

Ethan Mirsky and Andre DeHon. MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources. In Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, April 1996. [Anonymous FTP transit.ai.mit.edu:papers/matrix-fccm96.ps.Z].

Min67

Robert C. Minnick. A Survey of Microcellular Research. Journal of the ACM, 14(2):203-241, April 1967.

Min71

Robert Minnick. A Programmable Cellular Array. In Fifth Annual IEEE International Computer Society Conference: Hardware Software Firmware Trade-Offs, pages 25-26. IEEE, September 1971.

Mir96

Ethan Mirsky. Course-Grain Reconfigurable Computer. Master's thesis, Massachusetts Institute of Technology, 545 Technology Sq., Cambridge, MA 02139, June 1996. [Anonymous FTP transit.ai.mit.edu:papers/eamirsky-matrix-meng.ps.Z].

MKM +84

Koichiro Mashiko, Toshifumi Kobayashi, Hiroshi Miyamoto, Kazutami Arimoto, Yoshikazu Morooka, Masahiro Hatanaka, Michihiro Yamada, and Takao Nakano. A 70 ns 256K DRAM with Bit-Line Shield. IEEE Journal of Solid-State Circuits, 19(5), October 1984.

MKS +84

Amr Mohsen, Roger I. Kung, Carl J. Simonsen, Joseph Schutz, Paul D. Madland, Esmatz Z. Hamdy, and Mark T. Bohr. The Design and Performance of CMOS 256K Bit DRAM Devices. IEEE Journal of Solid-State Circuits, 19(5):610-620, October 1984.

MKS +92

Masato Matsumiya, Shoichiro Kawashima, Makoto Sakata, Masahiko Ookura, Toru Miyabo, Toru Koga, Kazuo Itabashi, Kazuhiro Mizutani, Hiroshi Shimada, and Noriyuki Suzuki. A 3.3-V 12-ns 16-Mb SRAM. IEEE Journal of Solid-State Circuits, 27(11):1497-1503, November 1992.

MMK +89

Fumio Miyaji, Yasushi Matsuyama, Yoshikazu Kanaishi, Katsunori Senoh, Takashi Emori, and Yoshiaki Hagiwara. A 25-ns 4-Mbit CMOS SRAM with Dynamic Bit-Line Loads. IEEE Journal of Solid-State Circuits, 24(5):1213-1218, October 1989.

MMM +91

Shigeru Mori, Hiroshi Miyamoto, Yoshikazu Morooka, Shigeru Kikuda, Makoto Suwa, Mitsuya Kinoshita, Atsushi Hachisuka, Hideaki Arima, Michihiro Yamada, Tsutomu Yoshihara, and Shimpei Kayano. A 45-ns 64-Mb DRAM with a Merged Match-Line Test Architecture. IEEE Journal of Solid-State Circuits, 26(11):1486-1492, November 1991.

MMN +90

Jiro Miyake, Toshinori Maeda, Yoshito Nishimichi, Joji Katsura, Takashi Taniguchi, Seiji Yamaguchi, Hisakazu Edamatsu, Shigeru Watari, Yoshiyuki Takagi, Kazuhiko Tsuji, Shigeo Kuninobu, Steve Cox, Douglas Duschatko, and Douglas MacGregor. A 40 MIPS (Peak) 64-bit Microprocessor with One-Clock Physical Cache Load/Store. In 1990 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pages 42-43. IEEE, February 1990.

MMS +84

Osamu Minato, Toshiaki Masuhara, Toshio Sasaki, Keizo Matsumoto, Yoshio Sakai, Tetsuya, and Hayashida. A 20 ns 64K CMOS Static RAM. IEEE Journal of Solid-State Circuits, 19(6), October 1984.

MNA +87

Koichiro Mashiko, Masao Nagatomo, Kazutami Arimoto, Yoshio Matsuda, Kiyohiro Furutani, Takayuki Matsukawa, Michihiro Yamada, Tsutomu Yoshihara, and Takao Nakano. A 4-Mbit DRAM with Folded-Bit-Line Adaptive Sidewall-Isolated Capacitor (FASIC) Cell. IEEE Journal of Solid-State Circuits, 22(5):643-650, October 1987.

MNH +91

Junji Mori, Masato Nagamatsu, Masashi Hirano, Shigeru Tanaka, Makoto Noda, Yoshiaki Yoyoshima, Kazuhiro Hashimoto, Hiroyuki Hayashida, and Kenji Maeguchi. A 10-ns 5454-b Parallel Structured Full Array Multiplier with 0.5m CMOS Technology. IEEE Journal of Solid-State Circuits, 26(4):600-606, April 1991.

MNS +96

Hiroshi Makino, Yasunobu Nakase, Hiroaki Suzuki, Hiroyuki Morinaka, Hirofumi Shinohara, and Koichiro Mashiko. An 8.8-ns 5454-Bit Multiplier with High Speed Redundant Binary Architecture. IEEE Journal of Solid-State Circuits, 31(6):773-783, June 1996.

MOT +87

Masataka Matsui, Takayuki Ohtani, Jun-Ichi Tsujimoto, Hiroshi Iwai, Azuma Suzuki, Katsuhiko Sato, Mitsuo Isobe, Kazuhiko Hashimoto, Mitsuchika Saitoh, Hideki Shibata, Hisayo Sasaki, Tadashi Matsuno, Jun-Ichi Matsunaga, and Tetsuya Iizuka. A 25-ns 1-Mbit CMOS SRAM with Loading-Free Bit Lines. IEEE Journal of Solid-State Circuits, 22(5):733-740, October 1987.

MSM +84

Jun-Ichi Miyamoto, Shinji Saito, Hiroshi Momose, Hideki Shibata, Koichi Kanzaki, and Tetsuya Iizuka. A High-Speed 64K CMOS RAM with Bipolar Sense Amplifiers. IEEE Journal of Solid-State Circuits, 19(5):557-564, October 1984.

MWA +96

James Montanaro, Richard Witek, Krishna Anne, Andrew Black, Elizabeth Cooper, Dan Dobberpuhl, Paul Donahure, Jim Eno, Alejandro Farell, Gregory Hoeppner, David Kruckemyer, Thomas Lee, Peter Lin, Liam Madden, Daniel Murray, Mark Pearce, Sribalan Santhanam, Kathryn Snyder, Ray Stephany, and Stephen Thierauf. A 160MHz 32b 0.5W CMOS RISC Microprocessor. In 1996 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pages 210-211. IEEE, February 1996.

MYM +87

Hiroshi Miyamoto, Tadato Yamagata, Shigeru Mori, Toshifumi Kobayashi, Shin-Ichi Satoh, and Michihiro Yamada. A Fast 256K4 CMOS DRAM with Distributed Sense and Unique Restore Circuit. IEEE Journal of Solid-State Circuits, 22(5):861-867, October 1987.

MYO +96

Hiroaki Murakami, Naoka Yano, Yukio Ootaguro, Yukio Sugeno, Maki Ueno, Yukinori Muroya, and Tsuneo Aramaki. A Multiplier-Accumulator Macro for a 45 MIPS Embedded RISC Processor. IEEE Journal of Solid-State Circuits, 31(7):1067-1071, July 1996.

NHK95

Kouhei Nadehara, Miwako Hayashida, and Ichiro Kuroda. A Low-Power, 32-bit RISC Processor with Signal Processing Capability and its Multiply-Adder, volume VIII of VLSI Signal Processing, pages 51-60. IEEE, 1995.

Nic90

John Nickolls. The Design of the MasPar MP-1: A Cost Effective Massively Parallel Computer. In Compcon Spring 90, pages 25-28. IEEE, 1990.

NNO +91

Takeshi Nagai, Kenji Numata, Masaki Ogihara, Mitsuru Shimizu, Kimimasa Imai, Takahiko Hara, Munehiro Yoshida, Yoshikazu Saito, Yoshiaki Asao, Shizuo Sawada, and Syuso Fujii. A 17-ns 4-Mb DRAM. IEEE Journal of Solid-State Circuits, 26(11):1538 ff., November 1991.

NSLKE86

Tobias G. Noll, Doris Schmitt-Landsiedel, Heinrich Klar, and Gerhard Enders. A Pipelined 300-MHz Multiplier. IEEE Journal of Solid-State Circuits, 21(3):411-416, June 1986.

NSS +86

Kazutaka Nogami, Takayasu Sakurai, Kazuhiro Sawada, Tetsunori Wada, Katsuhiko Sato, Mitsuo Isobe, Masakazu Kakumu, Shigeru Morita, Shunji Yokogawa, Masaaki Kinugawa, Tetsuya Asami, Kazuhiko Hashimoto, Jun-Ichi Matsunaga, Hiroshi Nozawa, and Tetsuya Iizuka. 1-Mbit Virtually Static RAM. IEEE Journal of Solid-State Circuits, 21(5):662-668, October 1986.

NTT +91

Yoshinobu Nakagome, Hitoshi Tanaka, Kan Takeuchi, Eiji Kume, Yasushi Watanabe, Toru Kaga, Yoshifumi Kawamoto, Fumio Murai, Ryuichi Izawa, Digh Hisamoto, Teruaki Kisu, Takashi Nishida, Eiji Takeda, and Kiyoo Itoh. An Experimental 1.5-V 64-Mb DRAM. IEEE Journal of Solid-State Circuits, 26(4):465 ff., April 1991.

Nut77

Gary J. Nutt. Microprocessor Implementation of a Parallel Processor. In Proceedings of the Fourth Annual International Symposium on Computer Architecture, pages 147-152. ACM, 1977.

OFW +87

Takashi Ohsawa, Tohru Furuyama, Yohji Watanabe, Hiroto Tanaka, Natsuki Kushiyama, Kenji Tsuchida, Yohsei Nagahama, Satoshi Yamano, Takeshi Tanaka, Satoshi Shinozaki, and Kenji Natori. A 60-ns 4-Mbit CMOS DRAM with Built-In Self-Test Function. IEEE Journal of Solid-State Circuits, 22(5):663-668, October 1987.

OHK +90

Takayuki Ootani, Shigeyuki Hayakawa, Masakazu Kakumu, Akira Aono, Masaaki Kinugawa, Hideki Takeuchi, Kazuhiro Noguchi, Tomoaki Yabe, Katsuhiko Sato, Kenji Maeguchi, and Kiyofumi Ochii. A 4-Mb CMOS SRAM with a PMOS Thin-Film-Transistor Load Cell. IEEE Journal of Solid-State Circuits, 25(5):1082-1091, October 1990.

OKH +84

Nobumichi Okazaki, Takaaki Komatsu, Naoya Hoshi, Kunihiko Tsuboi, and Takashi Shimada. A 16 ns 2K8 Full CMOS SRAM. IEEE Journal of Solid-State Circuits, 19(5):552-556, October 1984.

ONN +88

Hiroaki Okuyama, Takeshi Nakano, Shuichi Nishida, Etsuro Aono, Hisahiro Satoh, and Shigeru Arita. A 7.5-ns 32K8 CMOS SRAM. IEEE Journal of Solid-State Circuits, 23(5):1054-1059, October 1988.

OSS +95

Norio Ohkubo, Makoto Suzuki, Toshinobu Shinbo, Toshiaki Yamanaka, Akihiro Shimizu, Katsuro Sasaki, and Yoshinobu Nakagome. a 4.4 ns CMOS 5454-b Multiplier Using Pass-Transistor Multiplexer. IEEE Journal of Solid-State Circuits, 30(3):251-257, February 1995.

OTW +91

Yukihito Oowaki, Kenji Tsuchida, Yohji Watanabe, Daisaburo Takashima, Masako Ohita, Hiroaki Nakano, Shigeyoshi Watanabe, Akihiro Nitayama, Fumio Horiguchi, Kazunori Ohuchi, and Fujio Masuoka. A 33-ns 64-Mb DRAM. IEEE Journal of Solid-State Circuits, 26(11):1498-1505, November 1991.

Ple90

Plessey Semiconductors, Cheney Manor, Sindown, Wiltshire SN2 2QW, UK. ERA60100 Datasheet -- Electrically Reconfigurable Array, May 1990.

PML +89

A. Picco, J. C. Michalina, B. Laurier, D. Fuin, P. Menut, and JL. Laborie. The ST18940/41: An Advanced Single-chip Digital Signal Processors. In Proceedings of the 1989 IEEE International Symposium on Circuits and Systems, pages 1559-1562. IEEE, May 1989.

QC88

Le Quach and Richard Chueh. CMOS Gate Array Implementation of SPARC. In Digest of Papers COMPCON'88, pages 14-17. IEEE, Februrary 1988.

Ram93

Rambus Inc. Architectural Overview. Produce Literature, 1993. Rambus Inc., 2465 Latham Steet, Mountain View, CA 94040.

Raz94

Rahul Razdan. PRISC: Programmable Reduced Instruction Set Computers. PhD thesis, Harvard Univeristy, May 1994.

[Anonymous FTP ftp.eecs.harvard.edu:users/smith/theses/razdan-thesis.tar.gz].

RB91

Jonathan Rose and Stephen Brown. Flexibility of Interconnection Structures for Field-Programmable Gate Arrays. IEEE Journal of Solid-State Circuits, 26(3):277-282, March 1991.

RDB +94

Ehsan Rashid, Eric Delano, Michael Buckley, Jason Zheng, Francis Schumacher, Gordon Kurpanek, John Shelton, Tom Alexander, Nazeem Noordeen, Mark Ludwig, Alisa Scherer, Chaim Amir, Dan Cheung, Prasad Sabada, Ram Rajamani, Nick Fiduccia, Bill Ches, Kamyar Eshghi, Fred Eatock, Denny Renfrow, John Keller, Paul Ilgenfrizt, Ilan Krashinsky, Darryl Weatherspoon, Shrikant Ranade, Dave Goldberg, and William Byrg. A CMOS RISC CPU with On-Chip Parallel Cache. In 1994 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pages 210-211. IEEE, February 1994.

RFLC90

Jonathan Rose, Robert Francis, David Lewis, and Paul Chow. Architecture of Field-Programmable Gate Arrays: The Effect of Logic Block Functionality on Area Efficiency. IEEE Journal of Solid-State Circuits, 25(5):1217-1225, October 1990.

RK92

Dirk Reuver and Heinrich Klar. A Configurable Convolution Chip with Programmable Coefficients. IEEE Journal of Solid-State Circuits, 27(7):1121-1123, July 1992.

RPJ +84

Christopher Rowen, Steven Przbylski, Norman Jouppi, Thomas Gross, John Shott, and John Hennessey. A Pipelined 32b NMOS Microprocessor. In 1984 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pages 180-181. IEEE, February 1984.

RS92

Poornachandra B. Rao and Alexander Skavantzos. New Multiplier Designs Based on Squared Law Algorithms and Table Look-ups. In Conference Record of the Twenty-Sixth Asilomar Conference on Signals, Systems and Computers (volume 2), pages 686-690, October 1992.

RS94

Rahul Razdan and Michael D. Smith. A High-Performance Microarchitecture with Hardware-Programmable Functional Units. In Proceedings of the 27th Annual International Symposium on Microarchitecture, pages 172-180. IEEE Computer Society, November 1994. [Anonymous FTP ftp.eecs.harvard.edu:users/smith/papers/micro94.ps.gz].

RSV87

R. Rudell and A. Sangiovanni-Vincentelli. Multiple-Valued Minimization for PLA Optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits, 6(5):727-751, September 1987.

Rue89

Peter Ruetz. The Architectures and Design of a 20-MHz Real-Time DSP Chip Set. IEEE Journal of Solid-State Circuits, 24(2):338-348, April 1989.

SA90

Chip Sterns and Peng Ang. Yet Another Multiplier Architecture. In Proceedings of the IEEE 1990 Custom Integrated Circuits Conference, pages 24.6.1-4. IEEE, May 1990.

SAI +85

Hirofumi Shinohara, Kenji Anami, Katsuki Ichinose, Tomohisa Wada, Yoshio Kohno, Yuji Kawai, Yoichi Akasaka, and Shinpei Kayano. A 45-ns 256K CMOS Static RAM with Tri-Level Word Line. IEEE Journal of Solid-State Circuits, 20(5), October 1985.

Sch71

Mario R. Schaffner. A System with Programmable Hardware. In Fifth Annual IEEE International Computer Society Conference: Hardware Software Firmware Trade-Offs, pages 17-18. IEEE, September 1971.

Sch78

Mario R. Schaffner. Processing by Data and Program Blocks. IEEE Transactions on Computers, 27(11):1015-1028, November 1978.

SCLB84

Stanley E. Schuster, Barbara Chappell, Victor Di Lonardo, and Peter E. Britton. A 20 ns 64K (4K16) NMOS RAM. IEEE Journal of Solid-State Circuits, 19(5), October 1984.

Sei92

Charles L. Seitz. Mosaic C: An Experimental Fine-Grain Multicomputer. In A. Bensoussan and J.-P. Verjus, editors, Future Tendencies in Computer Science, Control and Applied Mathematics: Internantional Conference on the Occasion of the 25th Anniversary of INRIA, pages 69-85. Sprinter-Verlag, December 1992.

Seo94

Soon Ong Seo. A High Speed Field-Programmable Gate Array Using Programmable Minitiles. Master's thesis, University of Toronto, Ontario, Canada, 1994.

SFO +85

Shozo Saito, Syuso Fujii, Yoshio Okada, Shizuo Sawada, Satoshi Shinozaki, Kenji Natori, and Osamo Ozawa. A 1-Mbit CMOS DRAM with Fast Page Mode and Static Column Mode. IEEE Journal of Solid-State Circuits, 20(5), October 1985.

SGS +85

Lal C. Sood, James S. Golab, John Salter, John E. Leiss, and John J. Barnes. A Fast 8K8 CMOS SRAM With Internal Power Down Design Techniques. IEEE Journal of Solid-State Circuits, 20(5):941-950, October 1985.

SH89

Mark R. Santoro and Mark A. Horowitz. SPIM: A Pipelined 6464-bit Iterative Multiplier. IEEE Journal of Solid-State Circuits, 24(2):487-493, April 1989.

SHU +88

Katsuro Sasaki, Shoji Hanamura, Kiyotsugo Ueda, Takao Oono, Osamu Minato, Yoshio Sakai, Satoshi Meguro, Masayoshi Tsunematsu, Toshiaki Masuhara, Masaaki Kubotera, and Hiroshi Toyoshima. A 15-ns 1-Mbit CMOS SRAM. IEEE Journal of Solid-State Circuits, 23(5):1067-1073, October 1988.

SIS +90

Katsuro Sasaki, Koichiro Ishibashi, Katsuhiro Shimohigashi, Toshiaki Yamanaka, Nobuyuki Moriwaki, Shigeru Honjo, Shuji Ikeda, Atsuyoshi Koike, Satoshi Meguro, and Osamu Minato. A 23-ns 4-Mb CMOS SRAM with 0.2-A Standby Current. IEEE Journal of Solid-State Circuits, 25(5):1075-1081, October 1990.

SIU +92

Katsuro Sasaki, Koichiro Ishibashi, Kiyotsugo Ueda, Kunihiro Komiyaji, Toshiaki Yamanaka, Naotaka Hashimoto, Hiroshi Toyoshima, Fumio Kojima, and Akihiro Shimizu. A 7-ns 140-mW 1-Mb CMOS SRAM with Current Sense Amplifier. IEEE Journal of Solid-State Circuits, 27(11):1511-1518, November 1992.

SIY +89

Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Takashi Nishida, Katsuhiro Shimohigashi, Shoji Hanamura, and Shigeru Honjo. A 9-ns 1-Mbit CMOS SRAM. IEEE Journal of Solid-State Circuits, 24(5):1219-1225, October 1989.

SJ88

Naresh R. Shanbhag and Pushkal Juneja. Parallel Implementation of a 44 Multiplier Using Modified Booth's Algorithm. IEEE Journal of Solid-State Circuits, 23(4):1010-1013, August 1988.

SKI +88

Hiroshi Shimada, Shoichiro Kawashima, Hideo Itoh, Noriyuki Suzuki, and Takashi Yabu. A 45-ns 1-Mbit CMOS SRAM. IEEE Journal of Solid-State Circuits, 23(1):53-58, February 1988.

SKK +91

Katsuyuki Sato, Kanehide Kenmizaki, Shoji Kubono, Toshio Mochizuki, Hidetomo Aoyagi, Michitaro Kanamitsu, Soichi Kunito, Hiroyuki Uchida, Yoshihiko Yasu, Atsushi Ogishima, Sho Sano, and Hiroshi Kawamoto. A 4-Mb Pseudo SRAM Operating at 2.61V with 3-A Data Retention Current. IEEE Journal of Solid-State Circuits, 26(11):1556-1561, November 1991.

SKPS84

Robert Sherburne, Jr., Manolis Katevenis, David Patterson, and Carlo Sequin. A 32b NMOS Microprocessor with a Large Register File. In 1984 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pages 168-169. IEEE, February 1984.

SKS +93

Katsunori Seno, Kurt Knorpp, Lee-Lean Shu, Naoki Teshima, Hiroki Kihara, Hiroshi Sato, Fumio Miyaji, Minoru Takeda, Masayoshi Sasaki, Yoichi Tomo, Patrick Chuang, and Kazuyoshi Kobayashi. A 9-ns 16-Mb CMOS SRAM with Offset-Compenstated Current Sense Amplifier. IEEE Journal of Solid-State Circuits, 28(11):1119-1124, November 1993.

SKYH92

M. Shiraishi, M. Koizumi, A. Yamaguchi, and H. Hoike. User Programmable 16Bit 50ns DSP. In Proceedings of the IEEE 1992 Custom Integrated Circuits Conference, pages 6.4.1-6.4.4. IEEE, May 1992.

Sla95

Michael Slater. MicroUnity Lifts Veil on MediaProcessor. Microprocessor Report, 9(14):11 ff., October 23 1995. http://www.chipanalyst.com/report/report9_14/page11.html.

SLM +89

Ramautar Sharma, Alexander D. Lopez, John A. Michejda, Steven J. Hillenius, John M. Andrews, and Arnold J. Studwell. A 6.75-ns 1616-bit Multiplier in Single-Level-Metal CMOS Technology. IEEE Journal of Solid-State Circuits, 24(4):922-927, August 1989.

SMI +84

Takayasu Sakurai, Junichi Matsunaga, Mitsuo Isobe, Takayuki Ohtani, Kazuhiro Sawada, Akira Aono, Hiroshi Nozawa, Tetsuya IIzuka, and Susumu Kohyama. A Low Power 46 ns 256 kbit CMOS Static RAM with Dynamic Double Word Line. IEEE Journal of Solid-State Circuits, 19(5):578-584, October 1984.

SMK +94

Toshio Sunaga, Hisatada Miyatake, Koji Kitamura, Keishi Kasuya, Takaki Saitoh, Masahiro Tanaka, Norio Tanigaki, Yohtaro Mori, and Noritoshi Yamasaki. DRAM Macros for ASIC Chips. IEEE Journal of Solid-State Circuits, 30(9):1006-1014, September 1994.

SNT +84

Shun'ishi Suzuki, Masumi Nakao, Toshio Takeshima, Masaaki Yoshida, Masanori Kikuchi, Kunio Nakamura, Takeshi Mizukami, and Masayuki Yanagisawa. A 128K8 Bit Dynamic RAM. IEEE Journal of Solid-State Circuits, 19(5):624-626, October 1984.

Sny85

Lawrence Snyder. An Inquiry into the Benefits of Multigauge Parallel Computation. In Proceedings of the 1985 International Conference on Parallel Processing, pages 488-492. IEEE, August 1985.

SPA +95

Gene Shen, Niteen Patkar, Hisashige Ando, David Chang, Charles Chen, Chien Chen, Frank Chen, Per Forssell, John Gmuender, Takeshi Kitahara, Hungwen Li, David Lyon, Robert Montoye, Leon Peng, Sunil Savkar, Jonathan Sherred, Mike Simone, Ravi Swami, DeFroset Tovey, and Ted Williams. A 64b 4-Issue Out-of-Order Execution RISC Processor. In 1995 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pages 170-171. IEEE, February 1995.

SSL +92

Ellen M. Sentovich, Kanwar Jit Singh, Luciano Lavagno, Cho Moon, Rajeev Murgai, Alexander Saldanha, Hamid Savoj, Paul R. Stephan, Robert K. Brayton, and Alberto Sangiovanni-Vincentelli. SIS: A System for Sequential Circuit Synthesis. UCB/ERL M92/41, University of California, Berkeley, Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA 94720, May 1992.

SSN +92

Akinori Sekiyama, Teruo Seki, Shinji Nagai, Akihiro Iwase, Noriyuki Suzuki, and Masato Hayasaka. A 1-V Operating 256-kb Full-CMOS SRAM. IEEE Journal of Solid-State Circuits, 27(5):776-782, May 1992.

STN +93

Tadahiko Sugibayashi, Toshio Takeshima, Isao Naritake, Tatsuya Matano, Hiroshi Takada, Yoshiharu Aimoto, Koichiro Furuta, Mamoru Fujita, Takanori Saeki, Hiroshi Sugawara, Tatsunori Murotani, Naoki Kasai, Kentaro Shibahara, Ken Nakajima, Hiromitsu Hada, Takehiko Hamada, Naoaki Aizaki, Takemitsu Kunio, Eiichiro Kakehashi, Katsuhiro Masumori, and Takaho Tanigawa. A 30-ns 256-Mb DRAM with a Multidivided Array Structure. IEEE Journal of Solid-State Circuits, 28(11):1092-1098, November 1993.

STT +88

Hiroshi Shimada, Yoshinao Tange, Kazuo Tanimoto, Michio Shiraishi, Noriyuki Suzuki, and Toshio Nomura. An 18-ns 1-Mbit CMOS SRAM. IEEE Journal of Solid-State Circuits, 23(5):1073-1077, October 1988.

SUT +93

Katsuro Sasaki, Kiyotsugu Ueda, Koichi Takasugi, Hiroshi Toyoshima, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, and Nagatoshi Ohki. A 16-Mb CMOS SRAM with a 2.3m Single-Bit-Line Memory Cell. IEEE Journal of Solid-State Circuits, 28(11):1125-1130, November 1993.

SV93

Dinesh Somasekhar and V. Visvanathan. A 230-MHz Half-Bit Level Pipelinined Multiplier Using True Single-Phase Clocking. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1(4):415-422, December 1993.

SYN +94

Kazumasa Suzuki, Masakazu Yamashina, Takashi Nakayama, Masanori Izumikawa, Masahiro Nomura, Hiroyuki Igura, Hideki Heiuchi, Junichi Goto, Toshiaki Inoue, Youichi Koseki, Hitoshi Abiko, Kazuhiro Okabe, Atsuki Ono, Youichi Yano, and Hachiro Yamada. A 500MHz 32b 0.4m CMOS RISC Processor LSI. In 1994 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pages 214-215. IEEE, February 1994.

TEC +95

Edward Tau, Ian Eslick, Derrick Chen, Jeremy Brown, and Andre DeHon. A First Generation DPGA Implementation. In Proceedings of the Third Canadian Workshop on Field-Programmable Devices, pages 138-143, May 1995. [Anonymous FTP transit.ai.mit.edu:papers/dpga-proto-fpd95.ps.Z].

TFT +85

Yoshihisa Takayama, Shigeru Fujii, Tomoaki Tanabe, Kazuyuki Kawauchi, and Toshihiko Yoshida. A 1ns 20K CMOS Gate Array Series with Configurable 15ns 12K Memory. In 1985 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pages 196-197. IEEE, February 1985.

TJ85

Ronald T. Taylor and Mark G. Johnson. A 1-Mbit CMOS Dynamic RAM with a Divided Bitline Matrix Architecture. IEEE Journal of Solid-State Circuits, 20(5), October 1985.

TLB +90

Darius Tansalvala, Joel Lamb, Michael Buckley, Bruce Long, Sean Chapin, Jonathan Lotz, Eric Delano, Richard Luebs, Keith Erskine, Scott McMullen, Mark Forsyth, Robert Novak, Tony Gaddis, Doug Quarnstrom, Craig Gleason, Ehsan Rashid, Daniel Halperin, Leon Sigal, Harlan Hill, Craig Simpson, David Hollenbeck, John Spencer, Robert Horning, Hoang Tran, Thomas Hotchkiss, Duncan Weir, Donald Kipp, John Wheeler, Patrick Knebel, Jeffery Yetter, and Charles Kohlhardt. A 15 MIPS 32b Microprocessor. In 1990 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pages 52-53. IEEE, February 1990.

TNH +96

Toshinari Takayanagi, Kazutaka Nogami, Fumitoshi Hatori, Naoyuki Hatanaka, Makoto Takahashi, Makoto Ichida, Shinji Kitabayashi, Tatsuya Higashi, Mike Klein, John Thomson, Roger Carpenter, Ravi Donthi, Denny Renfrow, Jason Zheng, Liane Tinkey, Brandi Maness, Jim Battle, Steve Purcell, and Takayasu Sakurai. 350MHz Time-Multiplexed 8-port SRAM and Word-Size Variable Multiplier for Multimedia DSP. In 1996 IEEE International Solid-State Circuits Conference, Digst of Technical Papers, pages 150-151. IEEE, February 1996.

TNK +94

Yasuhiro Takai, Mamoru Nagase, Mamoru Kitamura, Yasuji Koshikawa, Naoyuki Yoshida, Yasuaki Kobayashi, Takashi Obara, Yukio Fukuzo, and Hiroshi Watanabe. 250 Mbytes/s Synchronous DRAM Using a 3-Stage-Pipelined Architecture. IEEE Journal of Solid-State Circuits, 29(4):426-431, April 1994.

TTK +90

Toshio Takeshima, Masahide Takada, Hiroki Koike, Hiroshi Watanabe, Shigeru Koshimaru, Kenjiro Mitake, Wataru Kikuchi, Takaho Tanigawa, Tatsunori Murotani, Kenji Noda, Kazuhiro Tasaka, Koji Yamanaka, and Kuniaki Koyama. A 55-ns 16-Mb DRAM with Built-in Self-Test Function Using Microprogram ROM. IEEE Journal of Solid-State Circuits, 25(4):903-910, August 1990.

TTS +86

Masahide Takada, Toshio Takeshima, Mitsuru Sakamoto, Toshiyuki Shimizu, Hitoshi Abiko, Takuya Katoh, Masanori Kikuchi, Sakari Takahashi, Yoshinori Sato, and Yasukazu Inoue. A 4-Mbit DRAM with Half-Internal-Voltage Bit-Line Precharge. IEEE Journal of Solid-State Circuits, 21(5), October 1986.

TTT +94

Satoru Tanoi, Yasuhiro Tanaka, Tetsuy Tanabe, Akio Kita, Toshio Inada, Ryoji Hamazaki, Yoshio Ohtsuki, and Masaru Uesugi. A 32-Bank 256-Mb DRAM with Cache and TAG. IEEE Journal of Solid-State Circuits, 29(11):1330-1336, November 1994.

TTU +91

Masao Taguchi, Hiroyoshi Tomita, Toshiya Uchida, Yasuhiro Ohnishi, Kimiaki Sato, Taiji Ema, Masaaki Higashitani, and Takashi Yabu. A 40-ns 64-Mb DRAM with 64-b Parallel Data Bus Architecture. IEEE Journal of Solid-State Circuits, 26(11):1493-1497, November 1991.

UKY84

Masaru Uya, Katsuyuki Kaneko, and Juro Yasui. A CMOS Floating Point Multiplier. IEEE Journal of Solid-State Circuits, 19(5):697-702, October 1984.

USO +93

Katsuhiko Ueda, Toshio Sugimura, Minoru Okamoto, Shinichi Marui, Toshihiro Ishikawa, and Mikio Sakakihara. A 16b Low-Power-Consumption Digital Signal Processor. In 1993 IEEE International Solid-State Circuits Conference, Digst of Technical Papers, pages 28-29. IEEE, February 1993.

VBB93

Joseph Varghese, Michael Butts, and Jon Batcheller. An Efficient Logic Emulation System. IEEE Transactions on Very Large Scale Integration (VLSI) Syatems, 1(2):171-174, June 1993.

Vil82

W. Vilkelis. Lead Reduction Among Combinational Logic Circuits. IBM Journal of Research and Development, 26(3):342-348, May 1982.

vMWvW +86

Jef van Meerbergen, Frank Welten, Frans van Wijk, Jan Stoter, Jos Huisken, Antoine Delaruelle, and Karel Van Eerdewijk. An 8 MIPS CMOS Digital Signal Processor. In 1985 IEEE International Solid-State Circuits Conference, Digst of Technical Papers, pages 84-85. IEEE, February 1986.

vN66

John von Neumann. Theory of Self-Reproducing Automata. University of Illinois Press, 1966. Compiled by Arthur W. Burks.

VPP +89

Peter Voss, Leo Pfennings, Cathal Phelan, Cormac O'Connell, Thomas Davies, Hans Ontrop, Simon Bell, and Roelof Salters. A 14-ns 256K1 CMOS SRAM with Multiple Test Modes. IEEE Journal of Solid-State Circuits, 24(4):874-881, August 1989.

VSCZ96

John Villasenor, Brian Schoner, Kang-Ngee Chia, and Charles Zapata. Configurable Computer Solutions for Automatic Target Recognition. In Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines. IEEE, April 1996.

WBEK +88

Todd Williams, Kenneth Beilstein, Badih El-Kareh, Roy Flaker, Gregory Gravenites, Robert Lipa, Hsing-San Lee, Joseph Maslack, John Pessetto, William F. Pokorny, Michael Roberge, and Harold Zeller. An Experimental 1-Mbit CMOS SRAM with Configurable Organization and Operation. IEEE Journal of Solid-State Circuits, 23(5):1085 ff., October 1988.

WBS +87

Karl Wang, Mark Bader, Vince Soorholtz, Richard Mauntel, Horacio Mendez, Peter Voss, and Roger Kung. A 21-ns 32K8 CMOS Static RAM with a Selectively Pumped p-Well Array. IEEE Journal of Solid-State Circuits, 22(5):704-712, October 1987.

WC96

Ralph D. Wittig and Paul Chow. OneChip: An FPGA Processor With Reconfigurable Logic. In Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, Los Alamitos, California, April 1996. IEEE Computer Society, IEEE Computer Society Press.

http://www.eecg.toronto.edu/ wittig/thesis.description.html.

WDW +85

Frank Welten, Antoine Delaruelle, Frans Van Wyk, Jef Van Meerbergen, Josef Schmid, Klaus Rinner, Karel Van Eedewijk, and Jan Wittek. A 2-m CMOS 10-MHz Microprogrammable Signal Processing Core with an On-Chip Multiport Memory Bank. IEEE Journal of Solid-State Circuits, 20(3):754-760, June 1985.

WH95

Michael J. Wirthlin and Brad L. Hutchings. A Dynamic Instruction Set Computer. In Peter Athanas and Ken Pocek, editors, Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, Los Alamitos, California, April 1995. IEEE Computer Society, IEEE Computer Society Press.

WHG94

Michael J. Wirthlin, Brad L. Hutchings, and Kent L. Gilson. The Nano Processor: a Low Resource Reconfigurable Processor. In Duncan A. Buell and Kenneth L. Pocek, editors, Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, pages 23-30, Los Alamitos, California, April 1994. IEEE Computer Society, IEEE Computer Society Press.

WHS +87

Tomohisa Wada, Toshihiko Hirose, Hirofumi Shinohara, Yuji Kawai, Kojiro Yuzuriha, Yoshio Kohno, and Shimpei Kayano. A 34-ns 1-Mbit CMOS SRAM Using Triple Polysilicon. IEEE Journal of Solid-State Circuits, 22(5):727-732, October 1987.

WOI +89

Shigeyoshi Watanabe, Yukihito Oowaki, Yasuo Itoh, Koji Sakui, Kenji Numata, Tsuneaki Fuse, Takayuki Kobayashi, Kenji Tsuchida, Masahiko Chiba, Takahiko Hara, Masako Ohta, Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, Takeshi Hamamoto, Kazunori Ohuchi, and Fujio Masuoka. An Experimental 16-Mbit CMOS DRAM Chip with a 100-MHz Serial READ/WRITE Mode. IEEE Journal of Solid-State Circuits, 24(3):763-770, June 1989.

Xil89

Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. The Programmable Gate Array Databook, 1989.

Xil91

Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. XC5200 FPGA Preliminary Prodcut Specification, version 4.0 edition, June 1991. http://www.xilinx.com/partinfo/5200.pdf.

Xil94a

Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. The Programmable Logic Data Book, 1989, 1994.

Xil94b

Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. The Programmable Logic Data Book, 1994.

Xil96

Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. XC6200 FPGA Advanced Product Specification, version 1.0 edition, June 1996. http://www.xilinx.com/partinfo/6200.pdf.

YFJ +87

Jeff Yetter, Mark Forsyth, William Jaffe, Darius Tanksalvala, and John Wheeler. A 15 MIPS 32b Microprocessor. In 1987 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pages 26-27. IEEE, February 1987.

YJY +90

Toshiaki Yoshino, Rajeev Jain, Paul Yang, Harvey Davis, Wanda Gass, and Ashwin Shah. A 100-MHz 64-Tap FIR Digital Filter in 0.8m BiCMOS Gate Array. IEEE Journal of Solid-State Circuits, 25(6):1494-1501, December 1990.

YKF +94

Nobuyuki Yamashita, Tohru Kimura, Yoshihiro Fujita, Yoshiharu Aimoto, Takashi Manabe, Shin'ichiro Okazaki, Kazuyuki Nakamura, and Masakazu Yamashina. A 3.84 GIPs Integrated Memory Array Processor with 64 Processing Elements and a 2-Mb SRAM. IEEE Journal of Solid-State Circuits, 29(11):1336-1343, November 1994.

YKK +84

Takashi Yamanaka, Shigeru Koshimaru, Osamu Kudoh, Yakashi Ozawa, Nobuyuoka, Hiroshiito, Hidehiro Asai, Nobuyuki Harashima, and Shinichi Kikuchi. A 25 ns 64K Static RAM. IEEE Journal of Solid-State Circuits, 19(5), October 1984.

YKMI88

Toshio Yamada, Hisakazu Kotani, Junko Matsushima, and Michihiro Inoue. A 4-Mbit DRAM with 16-bit Concurrent ECC. IEEE Journal of Solid-State Circuits, 23(1), February 1988.

YNH +91

Toshio Yamada, Yoshiro Nakata, Junko Hasegawa, Noriaki Amano, Akinori Shibayama, Masaru Sasago, Naoto Matsuo, Toshiki Yabu, Susumu Matsumoto, Shozo Okada, and Michihiro Inoue. A 64-Mb DRAM with Meshed Power Line. IEEE Journal of Solid-State Circuits, 26(11):1506-1510, November 1991.

YR95

Alfred K. Yeung and Jan M. Rabaey. A 2.4 GOPS Data-Drivern Reconfigurable Multiprocessor IC for DSP. In Proceedings of the 1995 IEEE International Solid-State Circuits Conference, pages 108-109. IEEE, February 1995.

YTN +85

Sho Yamamoto, Nobuyoshi Tanimura, Kouichi Nagasawa, Satoshi Meguro, Tokumasa Yasui, Osamu Minato, and Toshiaki Masuhara. A 256K CMOS SRAM with Variable Impedance Data-Line Loads. IEEE Journal of Solid-State Circuits, 20(5), October 1985.

YYN +90

Kazuo Yano, Toshiaki Yamanaka, Takashi Nishida, Masayoshi Saito, Katsuhiro Shimohigashi, and Akihiro Shimizo. A 3.8-ns CMOS 1616-b Multiplier Using Complementary Pass-Transistor Logic. IEEE Journal of Solid-State Circuits, 25(2):388-395, August 1990.