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List of Tables

• Survey of Processor Capacity
• Processor Capacity Summary
• Average Gate Evaluations/Datapath Bit
• Survey of VLIW Capacity
• VLIW Capacity Summary
• Survey of DSP Capacity
• DSP Capacity Summary
• Survey of Peak Memory Logic Capacity (SRAM)
• Survey of Peak Memory Logic Capacity (DRAM)
• Survey of Peak Memory Logic Capacity (Hybrid)
• Survey of Processor On-Chip Memory Capacity
• Survey of FPGA Capacity
• FPGA Capacity Summary
• Survey of SIMD Processor Capacity
• SIMD Processor Capacity Summary
• Example Vector Processor Capacity
• Vector Processor Capacity Summary
• Multimedia Processor Capacity
• Summary of Multimedia Processor Capacity
• Survey of Multi-Context FPGA Capacity
• Multi-Context FPGA Capacity Summary
• Survey of MIMD Processor Capacity
• Survey of Reconfigurable ALU Capacity
• Survey of Reconfigurable ALU Capacity
• General-Purpose Computational Capacity Summary
• Survey of Multiplier Capacity
• Sample Semi-Custom Multiplier Capacity
• Survey of Programmable Multiply Capacity
• Multiply Using Standard ALU Operations
• Yielded Multiply Capacity as a Function of Granularity
• Survey of Specialized Programmable Multiply Capacity
• Survey of FPGA-Implemented Processor Capacity
• FPGA 4-LUT Size
• Bits per 4-LUT
• FPGA Delay Breakdown
• Parameters for a Sampling of Contemporary Programmable Devices
• Configuration Bits -- Requirement Upper Bound v/s Actual
• 4-LUT in 2-ary Hierarchical Interconnect with
• Instruction Control Taxonomy
• Summary of Area Model Parameters
• for , ,
• Area for Instruction Control Sampling
• DPGA Prototype Implementation Characteristics
• Array Core Area Breakdown by Programmable Function
• DRAM Column Breakdown
• Memory Area Breakdown
• MCNC Circuit Benchmarks -- Latency Limited -- Two-Context DPGA Implemenation
• MCNC Circuit Benchmarks -- Latency Limited -- Four-Context DPGA Implemenation
• MCNC Circuit Benchmarks -- Latency Limited -- Context per Level DPGA Implemenation
• Multicontext Implementations of alu2 versus Throughput (LUTs)
• Multicontext Implementations of alu2 versus Throughput (Area)
• Multicontext Implementations of alu2 versus Throughput (Area Ratios)
• Benchmark Set Area -- Mapped Characteristics
• Selected Area/Throughput Points for Benchmark Set (1 Clock/Result)
• Selected Area/Throughput Points for Benchmark Set (10 Clock/Result)
• Selected Area/Throughput Points for Benchmark Set (20 Clock/Result)
• Full Partitioning of MCNC FSM Benchmarks (Area Target)
• Full Partitioning of MCNC FSM Benchmarks (Delay Target)
• Area and Delay versus Number of Contexts for cse FSM Benchmark (Area Target)
• Area and Delay versus Number of Contexts for cse FSM Benchmark (Delay Target)
• MCNC FSM Benchmarks LUTs v/s Number of Contexts (Area Target)
• MCNC FSM Benchmarks Area v/s Number of Contexts (Area Target)
• MCNC FSM Benchmarks Delay v/s Number of Contexts (Area Target)
• MCNC FSM Benchmarks Area Ratio v/s Number of Contexts (Area Target)
• MCNC FSM Benchmarks Delta Delay v/s Number of Contexts (Area Target)
• MCNC FSM Benchmarks Delay v/s Number of Contexts (Delay Target)
• MCNC FSM Benchmarks LUTs v/s Number of Contexts (Delay Target)
• MCNC FSM Benchmarks Area v/s Number of Contexts (Time Target)
• MCNC FSM Benchmarks Delta Delay v/s Number of Contexts (Delay Target)
• MCNC FSM Benchmarks Area Ratio v/s Number of Contexts (Delay Target)
• Memory Implementations for MCNC FSM Benchmarks
• Total Physial LUTs Required to Implement alu2 Benchmark
• Total Area Required to Implement alu2 Benchmark
• Area Ratios for alu2 Benchmark Implementation
• Average Ratios for Benchmark Set
• Average Ratios for Benchmark Set
• Average Ratios for Benchmark Set
• Average Ratios for Benchmark Set
• Average Ratios for Benchmark Set
• Average Ratios for Benchmark Set
• Average Ratios for Benchmark Set
• Average Ratios for Benchmark Set
• TSFPGA Subarray Parameters
• Modulo Context Sharing for MCNC Benchmarks
• Area Breakdown for Prototype MATRIX BFU Implementation
• MATRIX BFU Composition Estimate
• VSR Implementation Comparison
• RVF Implementation Comparison
• BFIR Implementation Comparison
• FIR Survey -- 88 multiply, 24-bit Accumulate
• FIR Survey -- 88 multiply, 16-bit Accumulate