Transit Notes
Catalogue
MIT Transit Project
Sat Mar 23 13:26:20 EST 1996
- TN#136
- DPGAs: A Step Toward Increased Computational Density
( in progress -- andre)
- TN#135
- Testing of a First-Generation
Dynamically Programmable Gate Array Prototype
( in progress -- edtau, andre)
- TN#134
- TSFPGA: A Fine-Grain Reconfigurable Architecture with
Time-Switched Interconnect
( in progress -- andre, kuang)
- TN#133
- An Introduction to the TSFPGA
( in progress -- kuang)
- TN#132
- MDL: A MATRIX Description Language
( complete -- beethovn)
- TN#131
- Reconfigurable Architectures and General-Purpose
Computing in the MOS VLSI Era
( in progress -- andre)
[tn131 PS link]
- TN#130
- MATRIX Micro-Architecture
( in progress -- eamirsky)
- TN#129
- DPGA Utilization and Application
( in progress -- andre)
[tn129 HTML link] [tn129 PS link]
- TN#128
- Entropy, Counting and Programmable Interconnect
( in progress -- andre)
[tn128 HTML link] [tn128 PS link]
- TN#127
- MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources
( coming soon... -- andre, eamirsky)
- TN#126
- Global Cooperative Computing: Pragmatics Revisited
( in progress -- beethovn)
- TN#125
- Hypercode
[tn125 PS link]
- TN#124
- Notes on VLSI Design: Lessons from the DPGA prototype
( in progress -- beethovn)
- TN#123
- Specialization Theory
( sidetracked... -- andre)
- TN#122
- Notes on Context Distribution
[tn122 HTML link] [tn122 PS link]
- TN#121
- Notes on Programmable Interconnect
[tn121 HTML link] [tn121 PS link]
- TN#120
- Notes on Integrating Reconfigurable Logic with DRAM
Arrays
[tn120 HTML link] [tn120 PS link]
- TN#119
- D/FPGAs in an ASIC Core Methodology
[tn119 HTML link] [tn119 PS link]
- TN#118
- Notes on Coupling Processors with Reconfigurable Logic
[tn118 HTML link] [tn118 PS link]
- TN#117
- Charles: Coprocessor and DRAM interfaces
( in progress -- beethovn)
- TN#116
- High Performance, Point-to-Point, Transmission Line
Signalling
( draft complete -- andre)
- TN#115
- Three-Dimensional Packaging for High-Performance
Interconnect in Large-Scale VLSI Systems
( draft complete -- andre)
- TN#114
- A First Generation DPGA Implementation
[tn114 HTML link] [tn114 PS link]
- TN#113
- Specialization versus Configuration
[tn113 HTML link] [tn113 PS link]
- TN#112
- A 1
CMOS Dynamically Programmable Gate Array
[tn112 HTML link] [tn112 PS link]
- TN#111
- Global Cooperative Computing
[tn111 HTML link] [tn111 PS link]
- TN#110
- A Proposal for Alternative Code:
a quasistatic-if-then-else and quasistatic variables
[tn110 HTML link] [tn110 PS link]
- TN#109
- Pragmatics and Starting Points for Global Cooperative
Computing ( watch for TN#126 -- update)
[tn109 HTML link] [tn109 PS link]
- TN#108
- Starting Point for Clever-Compiler Feedback ( in
progress -- andre, beethovn) [tn108 HTML link] [tn108 PS link]
- TN#107
- Guaranteeing Exactly-Once Delivery Semantics for Short-Haul, Fault-Tolerant Networks
[tn107 HTML link] [tn107 PS link]
- TN#106
- Informal Expected Blocking/Waiting Time Estimation
[tn106 HTML link] [tn106 PS link]
- TN#105
- Global Cooperative Computing
[tn105 HTML link] [tn105 PS link]
- TN#103
- Computational Quasistatics
[tn103 HTML link] [tn103 PS link]
- TN#102
- In-System Timing Extraction and Control through
Scan-Based, Test-Access Ports [tn102 HTML link] [tn102 PS link]
- TN#101
- The Clever Compiler: Proposal for a First-Cut Smart Compiler
( working copy available -- sc-developers) [tn101 HTML link] [tn101 PS link]
- TN#100
- DPGA-Coupled Microprocessors: Commodity ICs for the
Early 21st Century [tn100 HTML link] [tn100 PS link]
- TN#99
- Smart Compiler Advantages
[tn99 HTML link] [tn99 PS link]
- TN#98
- Smart Compiler Reading List ( working --
andre) [tn98 HTML link] [tn98 PS link]
- TN#97
- METRO: A Building Block for Fault-Tolerant,
Multiprocessor, Networks
- TN#96
- METRO: A Router Architecture for High-Performance,
Short-Haul Routing Networks [tn96 HTML link] [tn96 PS link]
- TN#95
- Unifying FPGAs and SIMD Arrays [tn95 HTML link] [tn95 PS link]
- TN#94
- Operating Environments for the 21st Century (
still in progress -- beethovn)
- TN#93
- Toward 21st Century Computing: Transit Perspective (
draft complete -- looking for feedback) [tn93 HTML link] [tn93 PS link]
- TN#92
- NIACT-ORBIT Datasheet [tn92 HTML link] [tn92 PS link]
- TN#91
- NOACT-ORBIT Datasheet [tn91 HTML link] [tn91 PS link]
- TN#90
- METROJR-ORBIT Datasheet [tn90 HTML link] [tn90 PS link]
- TN#89
- tcf2allegro board-design file formats
describes format of module and device files for feeding to allegro
pcboard tools [tn89 HTML link] [tn89 PS link]
- TN#88
- Potential Optimization Tricks for LiQuiD please
contribute -- andre, bdc, beethovn, cdr, stephend [tn88 HTML link] [tn88 PS link]
- TN#87
- Prospects for a Smart Compiler feedback sought --
andre [tn87 HTML link] [tn87 PS link]
- TN#86
- The Liquid Abstract Machine [tn86 HTML link] [tn86 PS link]
- TN#85
- Liquid Compiler Notes outdated, see tn86 [tn85 HTML link] [tn85 PS link]
- TN#84
- STING/Transit Collaboration Proposal [tn84 HTML link] [tn84 PS link]
- TN#83
- Overhead in ``Modern'' Operating Systems [tn83 HTML link] [tn83 PS link]
- TN#82
- Virtual Memory and Memory Viewpoints for Distributed
Systems [tn82 HTML link] [tn82 PS link]
- TN#81
- MLINK Programmer's Quick Reference [tn81 HTML link] [tn81 PS link]
- TN#80
- RAIL - Run Time Architecture Interface Layer ( working -- beethovn)
- TN#79
- TMAM - Transit/ METRO Active Messages ( usable --
see beethovn,jhbrown) [tn79 HTML link] [tn79 PS link]
- TN#78
- Distributed Liquid Implementation Strategies ( defunct) [tn78 HTML link] [tn78 PS link]
- TN#77
- Gdb/Nindy - Debugging and Run-time support [tn77 HTML link] [tn77 PS link]
- TN#76
- The Case of the Corrupted Acknowledgement [tn76 HTML link] [tn76 PS link]
- TN#75
- METRO LINK -- METRO Network Interface ( in
progress -- andre) [tn75 HTML link] [tn75 PS link]
- TN#74
- Boundary Scan Testing [tn74 HTML link] [tn74 PS link]
- TN#73
- METRO Architecture [tn73 HTML link] [tn73 PS link]
- TN#72
- Working With Actel Designs ( random bits -- andre) [tn72 HTML link] [tn72 PS link]
- TN#71
- Etherstation ( incomplete -- tanis)
- TN#70
- Analysis of Network Reconfiguration by Fault-Propagation [tn70 HTML link] [tn70 PS link]
- TN#69
- Transit Boundary-Scan Controller [tn69 HTML link] [tn69 PS link]
- TN#68
- RN2 Implementation Ideas [tn68 HTML link] [tn68 PS link]
- TN#67
- Transit Sbus Interface [tn67 HTML link] [tn67 PS link]
- TN#66
- TC1 Impedance Sequences [tn66 HTML link] [tn66 PS link]
- TN#65
- Automatic Impedance [tn65 HTML link] [tn65 PS link]
- TN#64
- Design and Performance of Multipath MIN Architectures
[tn64 HTML link] [tn64 PS link]
- TN#63
- Charles: Second Revision MBTA Node [tn63 HTML link] [tn63 PS link]
- TN#62
- Notes on Using Allegro ( ancient, but occassionally useful) [tn62 HTML link] [tn62 PS link]
- TN#60
- Using IEEE-1149 TAP in a Fault-Tolerant Architecture
[tn60 HTML link] [tn60 PS link]
- TN#59
- GPIB T-Station Quick Reference [tn59 HTML link] [tn59 PS link]
- TN#58
- Kendal: First Revision Daughter Cards [tn58 HTML link] [tn58 PS link]
- TN#57
- A Fast Static CMOS NOR Gate [tn57 HTML link] [tn57 PS link]
- TN#56
- Porting Nindy [tn56 HTML link] [tn56 PS link]
- TN#54
- Actel T-station Implementation ( obsolete; see
[tn63 HTML link] [tn63 PS link]) [tn54 HTML link] [tn54 PS link]
- TN#53
- Boundary Scan Software - Higher Level
[tn53 HTML link] [tn53 PS link]
- TN#52
- Node Prototype Motherboard Hardware [tn52 HTML link] [tn52 PS link]
- TN#51
- Multipath Network Fault-Tolerance Data ( incomplete --see Eran)
- TN#50
- Multipath Network Performance Data ( incomplete -- see Fred (ftchong))
- TN#49
- Master Boundary Scan Hardware [tn49 HTML link] [tn49 PS link]
( These were early
ideas. For something more complete see [tn69 HTML link] [tn69 PS link])
- TN#48
- Multipath Fault Tolerance in Multistage Routing Networks [tn48 HTML link] [tn48 PS link]
- TN#47
- Boundary Scan Software - Low Level
[tn47 HTML link] [tn47 PS link]
- TN#46
- TC: Onevolt Test Chip [tn46 HTML link] [tn46 PS link]
- TN#45
- RN1B Datasheet ( Update of TN#26 for REVB chip) [tn45 HTML link] [tn45 PS link]
- TN#44
- RN2 Proposal ( draft available but incomplete) [tn44 HTML link] [tn44 PS link]
- TN#43
- RN1net: an RN1 network simulator on the CM2
( incomplete -- see Fred (ftchong))
- TN#42
- Network Completeness [tn42 HTML link] [tn42 PS link]
- TN#41
- RNP: Fault Tolerant Routing Protocol ( complete ) [tn41 HTML link] [tn41 PS link]
- TN#40
- 1990 Project Highlights [tn40 HTML link] [tn40 PS link]
- TN#39
- MBTA: Wonderland Packaging [tn39 HTML link] [tn39 PS link]
- TN#38
- MBTA: Quick Overview [tn38 HTML link] [tn38 PS link]
- TN#37
- MBTA: Clocking Strategy [tn37 HTML link] [tn37 PS link]
- TN#36
- MBTA: Network Interface Implementation Notes (
working documentation -- very sketchy) [tn36 HTML link] [tn36 PS link]
- TN#35
- PAL Programming [tn35 HTML link] [tn35 PS link]
- TN#34
- MBTA: Software Model [tn34 HTML link] [tn34 PS link]
- TN#33
- Stack Packaging Components ( old sketch
never really completed -- updated by TN#115) [tn33 HTML link] [tn33 PS link]
- TN#32
- Practical Schemes for Fat-Tree Network Construction (
superceded by paper of same title appearing in the Advanced VLSI
Research Conference 1991: UC Santa Cruz)
[tn32 HTML link] [tn32 PS link] [FTP link]
- TN#31
- MBTA: Network Interface [tn31 HTML link] [tn31 PS link]
- TN#30
- MBTA: Node Bus Controller [tn30 HTML link] [tn30 PS link]
- TN#29
- Symbolic Wiring Routing Package ( see eran) [tn29 HTML link] [tn29 PS link]
- TN#28
- MBTA: Boot Sequence [tn28 HTML link] [tn28 PS link]
- TN#27
- MBTA: Network Initialization [tn27 HTML link] [tn27 PS link]
- TN#26
- RN1A Data Sheet [tn26 HTML link] [tn26 PS link]
- TN#25
- MBTA: Node Architecture [tn25 HTML link] [tn25 PS link]
- TN#24
- MBTA: Network Interface (Input) ( obsolete; see
[tn31 HTML link] [tn31 PS link])
- TN#23
- MBTA: Network Interface (Output) ( obsolete; see
[tn31 HTML link] [tn31 PS link])
- TN#22
- MBTA: Node Architecture Selection [tn22 HTML link] [tn22 PS link]
- TN#21
- MBTA: Message Formats [tn21 HTML link] [tn21 PS link]
- TN#20
- T-Station: The MBTA Host Interface [tn20 HTML link] [tn20 PS link]
- TN#19
- MBTA: Network Level Transactions [tn19 HTML link] [tn19 PS link]
- TN#18
- MBTA: Thoughts on Construction ( evolutionary
document -- working version available) [tn18 HTML link] [tn18 PS link]
- TN#17
- MBTA: Modular Bootstrapping Transit Architecture [tn17 HTML link] [tn17 PS link]
- TN#16
- Testing with the RN1 Slow Tester [tn16 HTML link] [tn16 PS link]
- TN#15
- The RN1 Slow Test Board Hardware [tn15 HTML link] [tn15 PS link]
- TN#14
- Analog Techniques for Adaptive Routing on
Interconnection Networks [tn14 HTML link] [tn14 PS link]
- TN#13
- Memory Transactions [tn13 HTML link] [tn13 PS link]
- TN#11
- Early Processor Ideas [tn11 HTML link] [tn11 PS link]
- TN#10
- Network Wiring Software [tn10 HTML link] [tn10 PS link]
- TN#9
- A Data to Processor Mapper ( see ftchong) [tn9 HTML link] [tn9 PS link]
- TN#8
- Practical Expander Networks with Analog Blocking Lines [tn8 HTML link] [tn8 PS link]
( see ftchong)
- TN#7
- A Generic Object-Oriented Network Simulator ( see
ftchong) [tn7 HTML link] [tn7 PS link]
- TN#6
- RN1: Forward Checksum [tn6 HTML link] [tn6 PS link]
- TN#5
- Global Perspective [tn5 HTML link] [tn5 PS link]
- TN#4
- Shared Randomness [tn4 HTML link] [tn4 PS link]
- TN#3
- Serialized Routing Component [tn3 HTML link] [tn3 PS link]
- TN#2
- Using the Network for Load Balancing on Parallel
Computers [tn2 HTML link] [tn2 PS link]
- TN#1
- RN1: Things to Improve Upon [tn1 HTML link] [tn1 PS link]
- TN#0
- Series Introduction [tn0 HTML link] [tn0 PS link]