Transit Note #10

Network Wiring Software

Andre DeHon

Original Issue: May 1990

Last Updated: Tue Nov 9 12:35:25 EST 1993

Problem

We have a good idea of how we want to wire our networks. In order to actually fabricate routing boards to implement these networks, we must produce a detailed wiring description for the board routing software. Since the task of reducing the high level network description to wiring details is tedious we need software to perform this translation.

Software Suite

Figure outlines the software needed to perform this translation. The three highlighted blocks at the left of the picture are the software needed. The board router shown on the right side represents existing software.

Symbolic Wire

Symbolic wire generates actual port to port interconnections between chips. This should take as inputs the network parameters:

As output, it generates a logical wiring list of the form:

Different network topologies will require different versions of symbolic wire. We definitely need a version that wires bidelta networks according to the specification of [DKM90] and [LM89]. We may eventually want a version of symbolic wire which will wire fat-tree stacks as described in [DeH90] using the principles of [DKM90] and [LM89].

Chip Placement

Chip Placement will start with the network interconnect topology specification generated by symbolic wire. It will assign the routing components in each layer to positions. The goal of chip placement is to minimize the maximum wire length in the network. For output, chip placement will generate a network description including connections of the form:

Detail Wire

Detail Wire takes the component positioning and interconnect generated by chip placement as input. Along with this, it takes a detailed description of the routing component. Detail wire will also get whatever additional wiring rules are necessary ( e.g. rotate 8 bit busses to the left by 2 bits between stages). With this information, it will generate a detailed network wiring list that includes every physical connection needed on the horizontal routing boards. The output of detailed wire should be in the appropriate format to be used directly by the board router.

Board Router

Once detail wire generates detailed wiring lists, the board router can route the actual boards for us. Once routed we will be ready to fabricate the pc-boards.

The board router available at the lab is Visula from Racal-Redac. We do not currently have documentation on the input format used by the router. Racal-Redac, however, has promised they will provide us with that information.

Priorities

  1. Symbolic Wire (Bidelta Networks)
  2. Detail Wire
  3. Chip Placement

The symbolic wiring description will also be needed for network simulations. Since simulations will precede fabrication of network routing boards, this will be needed first. For the small networks we are considering for initial construction, chip placement probably won't be too critical. The number of components to be placed will be moderately small and can be done by hand if absolutely necessary. Detailed wiring is a much more tedious task. The detailed wiring code should be developed first. Additionally, while symbolic and detailed wiring are well defined and well understood tasks, component placement is a more open ended task. As such, it will probably be best to defer spending much time on component placement until the other wiring software is functional.

Symbolic wiring software for fat-tree networks will also be of interest in the future. However, fat-tree networks are not in our critical path in the immediate future.

See Also...

References

DeH90
Andre DeHon. Fat-tree routing for transit. AI Technical Report 1224, MIT Artificial Intelligence Laboratory, 545 Technology Square, Cambridge MA 02139, April 1990.

DKM90
Andre DeHon, Thomas F. Knight Jr., and Henry Minsky. Fault-tolerant design for multistage routing networks. AI memo 1225, MIT Artificial Intelligence Laboratory, 545 Technology Square, Cambridge MA 02139, April 1990.

LM89
Tom Leighton and Bruce Maggs. Expanders might be practical: fast algorithms for routing around faults on multibutterflies. In 30th Annual Symposium on Foundations of Computer Science. IEEE, 1989.

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