Serialized Routing Component
Andre DeHon
Original Issue: April 1990
Last Updated: Tue Nov 9 12:27:38 EST 1993
RN1 is limited as much or more by pin count than logic/switching area. If we can reducing the pin requirements for an RN1 style routing requirement, we might be able to make an effectively wider routing component ( i.e. have a larger radix and/or dilation). Additionally, we might be able to afford additional pins for propagating routing information such as connection status and network loading (tn1).
If we serialize the data stream in and out of each input/output port, we can collapse the pin requirement from 9 pins per port to one. In fact, if we can afford the room internally, we could get away with making the the ports 16 or 32 bits wide instead of simply 8 bits.
We could go to a GaAs technology. Here we can integrate a serial
parallel converter into each input/output pad.
Gazelle Microcircuits currently has a pair of parallel
serial converters in GaAs which transmit data at 1Gbit/sec. (40 bit
parallel data clocked at 25MHz) [Gaz89]. This data rate is certainly
high enough to be interesting to us. The internal portion of the chip can
behave almost identically to the current RN1.
Alternately, we could consider serializing the internal portion of the router as well. If we can do logic and switching at comparable rates in GaAs and pipeline the internal architecture, we could get away with purely serial data paths.
In either case, we will lose some in latency since we must pipeline the
serial parallel conversion along with the switching.
The hope is that we will win more by being able to make wider routing
components.
With less constraints on pin allocation, we may be able to allocate some
pins to providing status and network information for adaptive routing
(tn1). If each input/output port had a single status pin which also
transmitted data serially in the same manner as the data, we should be able
to transmit plenty of data to do adaptive routing and early path
collapsing. This would make the total pin requirement for each
input/output port only 2. Thus
the current RN1 would be implemented with only
data pins instead of
and have a full backward
channel for network status information.
This serialization will also be a win in terms of wiring complexity. The number of interconnection wires will be reduced in the same manner as the pin count.
Additionally, this will prove quite useful when we need to go to optical communications. Certainly, this would be quite useful in the hollow cube structure described in [DeH90a].