One of our fundamental tenets is that one of the critical factors in engineering scalable massively parallel systems is the network interconnect latency. We have designed a network architecture(Transit Note #38), including packaging(Transit Note #39), a router and a preliminary node architecture(Transit Note #73). The project is in the process of assembling the first fully functional prototype of these designs.
The next phase of development includes migrating to standard cell silicon designs and work towards a functional stack packaging. In addition to the hardware development underway, we are expanding our efforts into providing highly efficient software substrates for both application and systems programming.
Our long term goals include development of a node architecture that better utilizes the network bandwidth and reduces node-level message handling, producing high-speed custom silicon router designs, fault-tolerant messaging layers and improved CAD tools. We hope to port certain portions of our tools to the machine to perform parallel logic and circuit simulation capabilities.
In our work we have become dissatisfied with contemporary computing models, operating systems, and compilation technology. To that end, we are undertaking a major thrust to reinvent computing which seeks to revise conventional computational paradigms.
For more information contact andre@ai.mit.edu.
Last Update: September 14th, 1993
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MIT Transit Project