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Non-Photolithographic Nanoscale Memory Density Prospects

Article by André DeHon, Seth Copen Goldstein, Philip J. Kuekes, and Patrick Lincoln appearing in IEEE Transactions on Nanotechnology, Volume 4, Number 2, Pages 215--228, Mar 2005.

Technologies are now emerging to construct molecular-scale electronic wires and switches using bottom-up self assembly. This opens the possibility of constructing nanoscale circuits and memories where active devices are just a few nanometers square and wire pitches may be on the order of 10 nanometers. The features can be defined at this scale without using photolithography. The available assembly techniques have relatively high defect rates compared to conventional lithographic integrated circuits and can only produce very regular structures. Nonetheless, with proper memory organization, it is reasonable to expect these technologies to provide memory densities in excess of 1011 bits/cm2 with modest active power requirements under 0.6W per Tb/s for random read operations.


N.b. The issue of deterministic addressing is detailed in Deterministic Addressing of Nanoscale Devices Assembled at Sublithographic Pitches.