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Contents

• Abstract
• Acknowledgments
• Contents
• List of Figures
• List of Tables
• Introduction and Background
  • Overview and Synopsis
    • Evolution of General-Purpose Computing with VLSI Technology
    • This Thesis
    • Reconfigurable Device Characteristics
    • Configurable, Programmable, and Fixed-Function Devices
    • Key Relations
    • New General-Purpose Architectures
      • DPGA
      • TSFPGA
      • MATRIX
    • Prognosis for the Future
  • Basics and Terminology
    • General-Purpose Computing
    • General-Purpose Computing Issues
      • Interconnect
      • Instructions
    • Programmables and Configurables
    • FPGA Introduction
    • Regular and Irregular Computing Tasks
    • Metrics: Density, Diversity, and Capacity
      • Functional Density
      • Functional Diversity -- Instruction Density
      • Data Density
  • Reconfigurable Computing Background
    • Successes of Reconfigurable Computing
      • Programmable Active Memories
      • Splash
      • PRISM
      • Logic Emulation
    • Lineage
    • Technological Enablers
• Empirical Review
  • Empirical Review of General Purpose Computing Architectures in the Age of MOS VLSI
    • Processors
      • Model
      • Capacity Provided
      • Example: Average Calculation
      • Example: Parity Calculation
    • VLIW Processors
    • Digital Signal Processors (DSPs)
    • Memories
      • Model
      • Capacity Provided
    • Field-Programmable Gate Arrays (FPGAs)
      • Model
      • Capacity Provided
      • Example: Average Calculation
      • Example: Parity Calculation
    • Vector and SIMD Processors
      • Model
      • Capacity Provided
      • Example: Average Calculation
      • Example: Parity Calculation
    • Multimedia Processors
    • Multiple Context FPGAs
    • MIMD Processors
    • Reconfigurable ALUs
      • Model
      • Capacity Provided
      • Example: Average Calculation
      • Example: Parity Calculation
    • Summary
  • Case Study: Multiply
    • Custom Multipliers
    • Semicustom Multipliers
    • General-Purpose Multiply Implementations
    • Hardwired Functional Units in ``General-Purpose Devices''
    • Multiplication Granularity
    • Specialized Multiplication
    • Summary
  • High Diversity on Reconfigurables
• Structure and Composition of Reconfigurable Computing Devices
  • Interconnect
    • Dominant Area and Delay
      • Fixed Area
      • Interconnect and Configuration Area
      • Delay
    • Problems with ``Simple'' Networks
      • Crossbars
      • Multistage Networks
      • Mesh Interconnect
    • Issues in Reconfigurable Network Design
    • Conventional Interconnect
    • Switch Requirements for FPGAs with 100-1000 LUTs
    • Channel and Wire Growth
      • Rent's Rule Based Hierarchical Interconnect Model
      • Wire Growth in Rent Hierarchy Model
      • Switch Growth in Rent Hierarchy Model
    • Network Utilization Efficiency
    • Interconnect Description
      • Weak Upper Bound
      • Structure Based-Estimates
      • Significance and Impact
      • Instruction Growth versus Interconnect Growth
    • Effects of Interconnect Granularity
      • Wiring
      • Switches
    • Summary
  • Instructions
    • General Case Example
    • Bits per Instruction
      • Processors
      • FPGAs
    • Compressing Instruction Stream Requirements
      • Wide Word Architectures
      • Broadcast Single Instruction to Multiple Compute Units
      • Locally Configure Instruction
      • Broadcast Instruction Identifier, Lookup in Local Store
      • Encode Length by Likelihood
      • Mode Bits for Early Bound information
      • Themes
    • Compressibility
    • Control Streams
    • Instruction Stream Taxonomy
    • Summary
  • RP-space Area Model
    • Model and Assumptions
      • FPGA Example
      • PADDI-2 Example
    • Peak Performance Density
    • Granularity
    • Contexts
    • Composition
    • Summary
• New Architectures
  • Dynamically Programmable Gate Arrays
    • DPGA Introduction
      • Traditional Pipelining for Throughput
      • Multicontext Implementation -- Temporal Pipelining
      • General Observations
    • Related Architectures
    • Realm of Application
      • Limited Throughput Requirements
        • Relative Processing Speeds
        • Fixed Functional Requirements
        • I/O Latency and Bandwidth
      • Latency Limited Designs
        • Cyclic dependencies
      • Temporally Varying or Data Dependent Functional Requirements
      • Multicontext versus Monolithic and Partial Reconfiguration
        • Tasks with limited throughput requirements
        • Latency limited tasks
        • Data varying logical functions
        • Infrequent temporal change
        • Large-grain, data-dependent blocks
        • Minor configuration edits
        • Reconfiguration Rate Taxonomy
    • A Prototype DPGA
      • Architecture
        • DRAM Memory
        • Array Element
        • Subarrays
        • Non-Local Interconnect
        • Local Decode
        • Global Interconnect
        • Programming
      • Implementation
        • Layout Inefficiencies
        • Memory
          • Area
          • Memory Timing
        • Crossbar Implementation
        • Timing
          • Pipelining
      • Component Operation
        • Inter-context Communication
        • Context Switching
        • DRAM Refresh
        • Background Load
      • Prototype Context Area Model
      • Prototype Conclusions
    • Circuit Evaluation
      • Levelization
      • Latency Limited Designs
        • Timing
        • Area
        • Area for Improvement
      • Limited Task Throughput
        • Area for Improvement
        • Time-Sliced Interleaving
    • Temporally Varying Logic -- Finite State Machines
      • Example
      • Full Temporal Partitioning
        • Timing
      • Partial Temporal Partitioning
      • Comparison with Memory-based FSM Implementations
      • Areas for Improvement
        • Timing
        • Partitioning
      • General Technique
    • Additional Application Styles
      • Multifunction Components
      • Utility Functions
      • Temporally Systolic Computations
    • Control
      • Segregation
      • Distribution
        • Hardwired Control
        • Configurable Control
        • Metaconfiguration
      • Source
        • Off-Chip
        • Local Dedicated Controller
        • Feedback Self Control
        • Self Control
    • Conclusions
  • Dynamically Programmable Gate Arrays with Input Registers
    • Input Registers
    • iDPGA Model
    • Example
    • Circuit Benchmarks: Input Depth
      • Mapping
      • Detailed Example: alu2
      • Average Characteristics
      • Area for Improvement
    • Other Input Retiming Models
      • Register File
      • Time Matching
    • Summary
    • Review
  • Time-Switched Field Programmable Gate Arrays
    • Time-Switched Input Registers
    • Switched Interconnect -- Folding
      • Subarray Structure
      • Interconnect Folding
    • Architecture
      • Array Element
      • Crossbar
      • Intra-Subarray Switching
      • Inter-Subarray Switching
      • I/O Connections
      • Array Control
    • Architecture Parameters
    • TSFPGA Implementation Estimates
      • Area
        • Focus Design Point
      • Timing
    • TSFPGA Fast Circuit Mapping
      • Timesteps and Contexts
      • Placement
      • Routing
      • Modulo Context Routing
    • Circuit Mapping
      • Context Compression
    • Related Work
    • Conclusions
    • Open Issues
  • MATRIX
    • MATRIX Concepts
    • MATRIX Architecture Overview
      • BFU
      • Network
      • Port Architecture
      • Port Contexts
        • Control
        • Global
      • Metaconfiguration Configuration
      • Time-Switching
      • Resource Deployment Granularity
      • Additional Information
    • Usage Example: Finite-Impulse Response Filter
      • Systolic
      • Microcoded
      • Custom VLIW (Horizontal Microcode)
      • VLIW/MSIMD
      • Comments
    • Flexible Instruction Distribution
      • Instruction Depth
      • Datapath Granularity
      • Instruction Streams
      • Control Streams
    • MATRIX Implementation
    • Building Block Efficiency
      • Memory
        • Versus Custom Memory
        • Versus Gate Array Memory
        • Versus Xilinx 4K Memory
      • Datapath Elements
        • Versus Hardwired ALU
        • Versus Systolic, Reconfigurable ALUs
        • ALU Bit Ops
        • Adder
        • Multiply
    • Image Processing Examples
      • VSR
      • RVF
      • BFIR
      • MFIR
      • Image Processing Summary
    • Summary
    • Area for Improvement
• Review and Extrapolation
  • Reconfigurable Processing Architecture Review
    • Special-Purpose Computing
    • General-Purpose Computing
    • Reconfigurable Computing Costs
    • Instructions
    • Interconnect
    • Degrees of Generality and Reconfigurability
    • FPGAs
    • Beyond FPGAs in the Reconfigurable Computing Space
    • Flexible Deployment of Instruction Resources
  • Projections
    • Role of Memory in Computational Devices
      • Memory for Instructions
        • Select Function
        • Shared Function
      • Memory for Retiming of Intermediate Data
      • Implications
    • Reconfiguration: A Technique for the Computer Architect
    • Projecting General-Purpose Computing onto RP-space
      • General Hazards
      • Processors, FPGAs, and RP-space
      • General-Purpose Computing Space
        • Hybrid
    • Trends and Implications for Conventional Architectures
      • Microprocessors
      • Multiprocessors
  • Review of Major Concepts
  • Terminology
• References
• About this document ...