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Seven Strategies for Tolerating Highly Defective Fabrication

Article by André DeHon and Helia Naeimi published in IEEE Design and Test of Computers, Volume 22, Number 4, pp. 306--315, July--August, 2005.

When we build devices with single-nanometer feature sizes and bottom-up assembly, defect rates may be in the 1--15% range---defect rates which are extremely high compared to conventional technologies. These high defect rates drive us to design fine-grained reconfigurable architectures which tolerate both defective wires and non-programmable crosspoints. We tolerate defective wires by exchanging good wires for defective ones. By matching the set of non-defective programmable junctions on each nanowire with the programmability needs of each logic component (e.g. product term), we can use nanowires even when they have defective crosspoints. These techniques can map designs in the Toronto20 benchmark set with 10% wire and junction defect rates in less than three times the area of defect-free fabrication.