Floating-Point Sparse Matrix-Vector Multiply for FPGAs (FPGA2005)


Floating-Point Sparse Matrix-Vector Multiply for FPGAs

Article by Michael deLorimier and André DeHon published in Proceedings of the International Symposium on Field-Programmable Gate Arrays (FPGA2005, February 20--22, 2005), p. 75--85.

Large, high density FPGAs with high local distributed memory bandwidth surpass the peak floating-point performance of high-end, general-purpose processors. Microprocessors do not deliver near their peak floating-point performance on efficient algorithms that use the Sparse Matrix-Vector Multiply (SMVM) kernel. In fact, it is not uncommon for microprocessors to yield only 10--20% of their peak floating-point performance when computing SMVM. We develop and analyze a scalable SMVM implementation on modern FPGAs and show that it can sustain high throughput, near peak, floating-point performance. For benchmark matrices from the Matrix Market Suite we project 1.5 double-precision Gflops/FPGA for a single virtex II 6000-4 and 12 double-precision Gflops for 16 Virtex IIs (750 Mflops/FPGA).

Paper

ACM Digital Library Entry
Author's local PDF copy smvm_fpga2005.pdf [300KB]