Transit Note #15c
RN1 Slow Test Board Hardware
Tim Kutscha
James Ooi
Original Issue: May 1990
Last Updated: Tue Nov 9 12:45:41 EST 1993
Overview
The Slow-Test board drives test-vectors through the RN1
chip and reads the data RN1 gives back. We will use a VME bus interface
to control the Slow-Tester.
Through Lisp primitives, the host machine will read and write data to
the tester
using VME bus memory locations relative to a user-defined base location. To
test RN1, we will latch 9-bit data bytes to the ports of RN1 that we wish to
drive. After latching the data, we will drive certain ports and clock RN1
using PAL logic and read
user-specified ports to verify the RN1's internal logic. Refer to (tn16)
for port addressing and programming information.
Description
The circuit consists of three basic subsystems:
- partial VME bus interface (primarily the address decoding, and
signal synchronization)
- Control circuitry
- RN1 chip interface (voltage level conversion to be added at a later
date when a new version of RN1 gets fabricated)
Subsystem 1 deals with interfacing the tester as a slave device on the VME
bus. Subsystem 2 decodes the RN1 address and data to determine which
tristates, latches and switches to enable, and subsystem 3 deals with driving
RN1, storing data in registers, and avoiding bus contention.
Subsystem 1: the VME bus interface logic
Anyone planning to modify the system should first read the VME bus specification
manual [Mot85] in the lab concerning VME bus read and write cycles. The
interface subsystem first
provides a current boost to the bus signals sufficient to drive 16 TTL
loads via 7, SN74ALS645A-1 8-bit transceivers (recommended in the VME specs). The
direction on these transceivers is
hardwired such that address lines, control strobes, address modifiers,
and /IACK are always driving the board from the bus. The transceivers
for the data lines are controlled by FSM signals /TRANSON and /B2A. One
tranceiver is used for /DTACK which either tri-states its output or drives it
to ground. Basically, the slave
must decode the address, address modifier, and /IACK lines before it
decides to respond to anything the master is doing. A 20v8 PAL decodes the
/AS, /IACK, address modifier and address lines. The single output from this
PAL goes into the other two 16v8 controller PALs. The controller PALs drive
the /DTACK line and other lines controlling the rest of the board by interpreting the
/WRITE, /DS0, and /DS1 signals from the bus.
Subsystem 2: the controller
The controller is composed
primarily of two 16v8 PALs which implement a finite state machine. See the
FSMC files and circuit diagrams attached to the end of this note for details
on the FSM. The controller board interprets four different types of actions
which include latching data to a particular port, reading 9-bit data from a
port, clocking RN1 while driving data into it, and writing data to the RN1
selector switches such as the swallows, reset, select and clkcntl.
In every bus cycle, as /DS0, /DS1 and the address confirmation from the 20v8
PAL assert, PAL #2 allows transfers on the data bus by asserting /TRANSON.
During this time, if /WRITE is low (on state) then PAL #2 drives B2A high,
allowing data to flow from the VME bus into the board. Similarly, if /WRITE
goes high (master reads slave) then PAL #2 drives B2A low, driving the VME
bus with data from the board.
When the bus tells the slave to latch data to a specific port, it performs a
write cycle with the port number contained in address lines A<4:1> and the
9-bit data to latch contained in D<8:0>. Address lines A05
and A06 must be low. When /DS0, /DS1 and the address line from the address
interpreter PAL become asserted, PAL #2 sees that /WRITE is low (master writing
to slave) and that A05 and A06 are high, so it asserts /GENLATCH. After
/GENLATCH asserts two '138 multiplexers interpret A01 through A04 and drive
one of the sixteen latch
lines low, activating the clock-enable on an '823 lying on one of the
four separate driver boards. This '823 flip-flop, corresponding to one of the
ports, reads D<8:0> and holds the 9-bit data on the next clock edge. PAL #1
waits three clock-cycles before asserting /DTACK, so the '823 has two edges to
get data. After PAL #1 asserts /DTACK, PAL #2 sees /DS0 or /DS1 rising so it
disables the clock-enable for the '823 and waits for the next cycle.
When the CPU wants to read data from a given port, the A<4:1> contain the
port number. The CPU starts a cycle with /WRITE high (master reads from slave).
After PAL #2 recognizes the address and sees /DS1 and /DS0 drop, it also sees
A05 and A06 low and /WRITE high, so it asserts the /DRIVEBUS flag. /DRIVEBUS
activates a pair of '138s similarly to /GENLATCH; however, this multiplexer
decodes A<4:1> and enables the outputs on one of the '825s located on an
external driver board. The '825s continually read the outputs from RN1 and
when their output enables assert, they drive a 9-bit data byte onto the VME
bus. PAL #1 waits three clock-cycles again before asserting /DTACK. Both
PALs fall back to idle states when /DS1 or /DS0 rise until the next bus cycle.
After latching data to several input ports on RN1, the host computer should
write to the tester while driving address
line A05 high. A<4:1> don't matter now; however, the bits in the data lines
D<15:0> tell the controller board which ports to drive. D0 corresponds to the
first port on connector A and so on. Therefore, if you write to the tester
and drive A05 high with the hex number x0034 (0000000000110100 binary) on the
data bus, ports 3, 5 and 6 on the tester would get driven. Keep in mind that
the ports on the tester do not correspond directly to the ports on RN1. See
(tn16) for information on which tester ports drive which RN1 ports.
After /DS1, /DS0 and the address confirmations assert, PAL #1 starts cycling
through the stages of its finite state machine program. On the first clock
edge, PAL #1 asserts ENDAT which is NANDed with all
the data lines. The outputs of these 7400 NAND gates enable the outputs on
certain '823s which should have previously had 9-bit data latched to them. On
clock edge two, PHI1 asserts. PHI2 asserts on the fourth clock edge after
PHI1 drops on the third clock edge. On the fifth clock cycle, PHI2 and ENDAT
drop while /DTACK asserts. After /DS0 or /DS1 rise again, /DTACK de-asserts
and the PALs fall into idle state until the next bus cycle.
If the CPU wants to change the swallows on RN1 or change the selector
switches, it asserts address line A06 instead of A05 and the bits containing
the switch data exist on data lines D0-D15. Refer to the Software reference
(tn16) for more information. If PAL #2 sees /WRITE low
and A06
high after seeing /DS0, /DS1 and the address confirmation assert, then it
starts a finite state machine sequence which asserts RLATCH for one clock
cycle. PAL #1 delays three cycles before asserting /DTACK, so the data on lines
D<15:0> is still stable for another two clock cycles while the pair '373s
capture the switching data off the data bus. As in other functions, both
control PALs fall back into an idle state when /DS0 or /DS1 go high,
signalling the end of the bus cycle.
Subsystem 3: the chip interface
Each individual port has
two chips to go with it, a 9-bit wide flip-flop with clock enable and tri-state,
and a 9-bit tristate
buffer whose outputs drive (or don't drive) the data bus. The flip-flop with
clock enable (an LS823) functions to latch the input data for the chip if
that port needs it.
Five and One volt configurations
The first version of RN1
utilizes 5 volt pads; however, the next version of RN1 uses 1 volt customized
pads. Fortunately, since the controller board fans out to four external
driver boards through 40-pin ribbon cable, we can just change the four
external boards with new ones containing 5 to 1 volt ECL converters or other
conversion chips.
Hardware Discussion
The slow-tester has a control board and four chip
interface boards, one for each quadrant of the chip, where each quadrant
contains four 9-bit wide data ports.(tn26) The control board plugs into a triple
height VME backplane inside the host computer.
The top VME connector
(P1) contains all the address lines, data lines, and status signals while
the middle connector only provides additional power and grounds for the
tester control board. The third, lower connector is unused. The
control board can run totally off the single upper port if necessary.
In the upper-left drawer of the cabinet just inside the seventh floor lab
there exists a wire-wrapped P1 VME bus extender for the controller board and
other debugging circuits such as a PAL tester and hex display.
Four 40-pin flat ribbon cables
come out of the back of the controller board and connect to the four interface
boards driving RN1. The connectors on the control board are labeled A through
D which correspond to the labels on the chip testhead (see Fred Drenckhahn for
info). The 40-pin ribbon cables contain the data lines D<8:0> from the VME bus,
control signals for latching data to a port, signals to read and drive RN1,
and a system clock to drive the flip-flops. The cable contains four RN1
control signals such as the swallows, reset, select, clkcntl, and the two
chip clocks (phi1 and phi2). Every third wire in the ribbon cable is grounded
to cut noise with the exception of the clock which has ground wires on either
side of it. The four interface boards require their own 5V power supply which
not only drives data to RN1 but also powers RN1. The 1V and 5V power input
pads on the interface board should be jumpered together for the first version
of RN1 since it only uses a 5V interface voltage. Although each side of
RN1 is essentially the same, the correct port should be connected to the
correct side of RN1 for software purposes.
Since the ribbon cable from the control board to the interface boards is long,
the system clock drives all the inputs on a hex inverting buffer.
Two outputs on the hex inverter drive the on board PALs while
the other four drive the inputs of two SN75452B dual high-current line drivers
to drive the system clocks to the four remote boards. The driven clock
signals are terminated on the external boards by a voltage divider pulling
up the clock to 3 volts with 200 and 300 ohm resistors.
The swallows and RN1 control signals are controlled totally by software
for ease of use. The addressing system is controlled by a programmed 20v8
PAL instead of physical jumpers which often create noise and are hard to work
with. Address lines A01 through A06 control the functions of the control
board, leaving the remaining nine address lines to distinguish the controller
board from other slave boards on the VME bus. To change the address, edit the
address.fsm file, adding and deleting negation slashes in the logic
equation and recompile it, reprogramming the 20v8 as previously discussed.
Programmable Logic
The Slow-Test board uses two 16v8 PALs for
controlling the logic signals and one 20v8 PAL for confirming port addressing
information. The 16v8 PAL's need to be programmed with the FSM files in the
transit/doc/notes/tn15/ directory ( tester1.fsm tester2.fsm
address.fsm).
Since both 16v8 PAL's have the same inputs, We needed to create two PAL files
for the logic.
N.B. FSMC is Finite State Machine Compiler which is part of the
6.111 course software. To use it at the A.I. Lab, add the following lines to
your .cshrc.mine file:
setenv FSM_P_DIR /home/ar/transit/src/fsmc/proto
setenv FSM_C_FIL /home/ar/transit/src/fsmc/config
Also add /home/ar/transit/${MACHINE} to your PATH.
Then type in the following lines to compile an .FSM file (tester1):
This will generate tester1.jed and tester1.pal from tester1.fsm.
To program the PAL's, use the Unisite universal programmer. You should first FTP to alpha-bits
and put the JED files onto the Unisite PC hard-drive. Then type PROGRAM
from
the directory where your files are on the PC. Boot up the Unisite with the
systems software disk and then put in the algorithms disk. Select the proper
PAL device from the menus. To transfer a .JED file to the Unisite for
programming, select the other option, then transfer data, and finally
download. Download the file to RAM through the terminal (not remote) port.
Go to the file window at the bottom of the screen using the cursor keys and
type: TRANSFER filename.jed and hit Return twice. Go back to the main
menu with F1 and program the PAL after you put it in the Unisite.
You can also program the PAL's on the Zap-a-PAL computer in the seventh floor
hardware lab. Run the ZAPAL program in the ZAPNEW directory. You must first
FTP your JED files to floppy disk on the sixth or ninth floor.
The ZAPAL program is menu driven, so you should be able to run it with little
trouble. Additional documentation also exists in
transit/doc/random/pal in the file zap-a-pal.txt.
VME bus Specifications
Remember that:
- There are only 31 address lines, from A01 to A31, so short mode is
only 15 bits of address, normal only 23 and extended only 31. No A0 is needed
because the data is two bytes wide and the LWORD flag distinguishes between
the two bytes if the slave board is in 8 bit mode.
- Every bus line has a pullup resistor to +5V inside the CPU itself (not
on the slave card).
- The slave must make sure that the /IACK line is high when looking at
the bus so that the bus is NOT signalling an interrupt request.
- The slave must look at the address modifier lines to interpret the
type of data sent/expected (i.e. 8-bit, 16-bit data or 16-bit, 32-bit
addressing). The Slow-Tester needs an address modifier of hex 29 to work.
- The male connectors on the slave board, which plug into the backplane
have 96-pins in an unstaggered, 3 column configuration.
- basic sequence of action:
- Master makes sure the broadcast address is stable and then asserts /AS,
/IACK should be high and /RW should indicate whether the master intends to
drive or read data on the bus.
- Slave decodes address and determines if the address is calling it.
- The master asserts /DS0 and /DS1 in reasonably rapid succession
although not necessarily in that order.
- When the master writes to the slave (/RW high), the slave uses the data
and then asserts /DTACK when finished.
- When the master sees that /DTACK has been asserted, he sends
/DS0 and /DS1 high after which the slave must tri-state /DTACK so the
bus can start another cycle.
- On a read, the slave drives the data lines on the bus when /DS0 and /DS1
go low and asserts /DTACK when the data is valid.
- Likewise with a read, the slave tri-states the data lines when the
master drives /DS0 and /DS1 high and waits for the next cycle.
- All other lines dealing with more complex options can be ignored.
Although we mentioned LWORD before, we are reading 16-bits off the bus so
LWORD becomes pointless.
The PC Board
I make pc boards in the following way:
- In Douglas Schematic, make a report from the module menu.
- Edit the report in a text editor to remove the ground and +5V nodes, but
save these nodes somewhere for future reference. Edit report to use
whatever routing commands you want. Routing commands are documented in
the autorouter documentation.
- Go to the layout program, edit footprint library by adding all
the footprints for the chips
being used. Save file. Open new double-sided file. Convert file to a label file
via menu option of same name. Open edited footprint library. Select
footprints being used. Add them to your
palette. Place footprints on the new double-sided file.
Name the footprints the same name as the report gives the
corresponding chip name. Save board while in parts placement mode.
- Start autorouter. The command file is the report. The layout
file is the thing you just made in item 2. Let it run. The output file
is the finished pc board. Add power and ground connections to inner
layers in the layout program by putting shorting bars accross the power and
ground terminals . Check RouteReport to see if routing was complete and for
errors. Read the Douglas manuals above the Macintosh computer in the
lab for more information on the layout program and shorting bars.
- You may skip steps 1 through 4 if you simply hand route the entire board
in Douglas Layout (which is what I actually did). I found that the autorouter
was too confusing and difficult to use. It often created a huge mess of wires
on the board that I couldn't follow. Unless you program the Autorouter with
an excellent strategy, the final routed board won't be complete and the
trances will be hard to follow. By
hand routing, I could lay out the wires neatly and in an organized pattern.
- Use the CAM Exchange program to order the boards from Douglas. Unplug
Fred Drenckahn's office phone line and plug in the one for the 1200 baud modem
to upload the file. Replace Fred's office line immediately after you are
finished.
The board is a four layer one with normal signals on the outsides, and
ground and VCC planes in the middle.
The system was laid out using the Douglas Professional System. Source
files are on the Mac II in the lab in the CAD-Current TB data folder. The
schematic for the control board is called TESTBOARD3.0 (use the
latest version) and the schematic for the chip interface boards are called
TB 1 side 3.0 (use the latest version). Generating a report from these
schematic files is all that is needed for use of the autorouter. Since
I hand routed both boards, the finished, routed boards are named CONT
BOARD L 8.0 for the controller board and CONT BOARD R 8.0 for the interface
boards. While the controller board is sized for a triple-height XL1200 VME
bus backplane, the four interface boards can be of any size and are currently
as small as I could get them to save on fabrication costs.
The CAM Exchange
program only gives correct quotes for two layer boards so you should roughly
double the price to get a four-layer board quote.
When you use the CAM Exchange program, be sure to explicitly state that
you want a four-layer board with internal ground and VCC planes.
The shorting bars will automatically
fall to the internal power and ground layers during fabrication so they don't
short out your surface traces. Board quotes are based on total board area,
number of holes and total trace length, so keep your boards small and limit
the number of holes if possible. If you hand route your board, you should
run the layout file through the autorouter without any routing commands to
compress the file. I was able to reduce a 300k file down to 30k bytes.
Unfinished Business
- Design and fabricate the interface boards using ECL chips for the final
version of RN1 which uses the one volt inverting pads. The programming will
also have to be altered to handle the inverted clocks and data lines.
See Also...
- VME bus specifications [Mot85]
- RN1 chip specifications (tn26)
- Programming the tester in lisp [Kut90]
References
- Kut90
-
Tim Kutscha.
Testing with the RN1 Slow Tester.
Transit Note 16, MIT Artificial Intelligence Laboratory, May 1990.
[tn16 HTML link] [tn16 FTP link].
- Min90
-
Henry Q. Minsky.
RN1 Data Router.
Transit Note 26, MIT Artificial Intelligence Laboratory, July 1990.
[tn26 HTML link] [tn26 FTP link].
- Mot85
-
Motorola Semiconductor Products Inc., P.O. Box 20912 Phoenix, AZ 85036.
VMEbus Specification Manual, Revision C, February 1985.