Fault-Tolerant Sub-lithographic Design with Rollback Recovery
Helia Naeimi and André DeHon
Nanotechnology,
Volume 19, Number 11, Article 115708, March 19, 2008.
Shrinking feature sizes and energy levels coupled with high clock rates
and decreasing node capacitance lead us into a regime where transient
errors in logic cannot be ignored. Consequently, several recent studies
have focused on feed-forward spatial redundancy techniques to combat these
high transient fault rates. To complement these studies, we analyze
fine-grained rollback techniques and show that they can offer lower spatial
redundancy factors with no significant impact on system performance for
fault rates up to one fault per device per ten million cycles of operation
(Pf=10-7) in systems with 1012 susceptible
devices. Further, we concretely demonstrate these claims on nanowire-based
Programmable Logic Arrays. Despite expensive rollback buffers and
general-purpose, conservative analysis, we show the area overhead factor of
our technique is roughly an order of magnitude lower than a gate-level
feed-forward redundancy scheme.
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