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FPT2014
Albert Kwon, Kaiyu Zhang, Perk Lun Lim, Yuchen Pan, Jonathan M. Smith, and André DeHon. RotoRouter: Router Support for Endpoint-Authorized Decentralized Traffic Filtering to Prevent DoS Attacks. In Proceedings of the IEEE International Conference on Field-Programmable Technology, December, 2014. [Abstract and Paper Link]

FCCM2014c
Edin Kadric, Kunal Mahajan, and André DeHon. Kung Fu Data Energy---Minimizing Communication Energy in FPGA Computations. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, May, 2014. [Abstract and Paper Link]

FCCM2014b
Edin Kadric, Kunal Mahajan, and André DeHon. Energy Reduction through Differential Reliability and Lightweight Checking. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, May, 2014. [Abstract and Paper Link]

FCCM2014a
Benjamin Gojman and André DeHon. GROK-INT: Generating Real On-chip Knowledge for Interconnect Delays Using Timing Extraction. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, May, 2014. [Abstract and Paper Link]

FPGA2014
André DeHon. Wordwidth, Instructions, Looping, and Virtualization---The Role of Sharing in Absolute Energy Minimization. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 189--198, February, 2014. [Abstract and Paper Link]

POPL2014
Arthur Azevedo de Amorim, Nathan Collins, André DeHon, Delphine Demange, Cătălin Hriţcu, David Pichardie, Benjamin C. Pierce, Randy Pollack, Andrew Tolmach. In Proceedings of the ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, January 2014. [Abstract and Paper Link]

FPT2013
André DeHon and Nikil Mehta. Exploiting Partially Defective LUTs: Why You Don't Need Perfect Fabrication. In Proceedings of the IEEE International Conference on Field-Programmable Technology, December, 2013. (outstanding paper award) [Abstract and Paper Link]

CCS2013
Albert Kwon, Udit Dhawan, Jonthan M. Smith, Thomas F. Knight, Jr. and André DeHon. Low-Fat Pointers: Compact Encoding and Efficient Gate-Level Implementation of Fat Pointers for Spatial Safety and Capability-based Security. In Proceedings of the ACM Conference on Computer and Communications Security, November, 2013. [Abstract and Paper Link]

ARITH2013
Edin Kadric, Paul Gurniak, and André DeHon. Accurate Parallel Floating-Point Accumulation. In Proceedings of the IEEE Symposium on Computer Arithmetic, April, 2013. [Abstract and Paper Link]

FPGA2013a
Benjamin Gojman, Sirisha Nalmela, Nikil Mehta, Nicholas Howarth, and André DeHon. GROK-LAB: Generating Real On-chip Knowledge for Intra-cluster Delays using Timing Extraction. In Proceedings of the International Symposium on Field Programmable Gate Arrays, February, 2013. [Abstract and Paper Link]

FPGA2013b
Udit Dhawan and André DeHon. Area-Efficient Near-Associative Memories on FPGAs. In Proceedings of the International Symposium on Field Programmable Gate Arrays, February, 2013. [Abstract and Paper Link]

FPGA2013c
André DeHon. Location, Location, Location---The Role of Spatial Locality in Asymptotic Energy Minimization. In Proceedings of the International Symposium on Field Programmable Gate Arrays, February, 2013. [Abstract and Paper Link]

FPT2012
Yutian Huan and André DeHon. FPGA Optimized Packet-Switched NoC using Split and Merge Primitives. In Proceedings of the IEEE International Conference on Field-Programmable Technology, December, 2012. [Abstract and Paper Link]

AHNS2012
Udit Dhawan, Albert Kwon, Edin Kadric, Catalin Hritcu, Benjamin C. Pierce, Jonathan M. Smith, Gregory Malecha, Greg Morrisett, Thomas F. Knight, Jr., Andrew Sutherland, Tom Hawkins, Amanda Zyxnfryx, David Wittenberg, Peter Trei, Sumit Ray, Greg Sullivan, André DeHon. Hardware Support for Safety Interlocks and Introspection. In Proceedings of the SASO Workshop on Adaptive Host and Network Security, September 14, 2012. [Abstract and Paper Link]

FPGA2012
Nikil Mehta and André DeHon. Limit Study of Energy & Delay Benefits of Component-Specific Routing. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 97--106, February, 2012. [Abstract and Paper Link]

TRCAD2012
Nachiket Kapre and André DeHon. SPICE2: Spatial Processors Interconnected for Concurrent Execution for Accelerating the SPICE Circuit Simulator Using an FPGA. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 31, Number 1, pp. 9--12, DOI: 10.1109/TCAD.2011.2173199, January, 2012. [Abstract and Paper Link]

TRETS2011
Raphael Rubin and André DeHon. Choose-Your-Own-Adventure Routing: Lightweight Load-Time Defect Avoidance. In ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 4, Number 4, DOI: 10.1145/2068716.2068719, December, 2011. [Abstract and Paper Link]

FPT2011
Nachiket Kapre and André DeHon. VLIW-SCORE: Beyond C for Sequential Control of SPICE FPGA Acceleration. In Proceedings of the IEEE International Conference on Field-Programmable Technology, December, 2011. (best paper) [Abstract and Paper Link]

TAAS2011
Michael deLorimier, Nachiket Kapre, Nikil Mehta, and André DeHon. Spatial hardware implementation for sparse graph algorithms in GraphStep. In ACM Transactions on Autonomous and Adaptive Systems (TAAS), Volume 6, Number 3, DOI: 10.1145/2019583.2019584, September, 2011. [Abstract and Paper Link]

IJRC2011
Nachiket Kapre and André DeHon. An NoC Traffic Compiler for Efficient FPGA Implementation of Sparse Graph-Oriented Workloads. In International Journal of Reconfigurable Computing, Volume 2011, Article ID 745147, DOI: 10.1155/2011/745147, March, 2011. [Abstract and Paper Link]

FPGA2011
Raphael Rubin and André DeHon. Timing-Driven Pathfinder Pathology and Remediation: Quantifying and Reducing Delay Noise in VPR-Pathfinder. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 173--176, February, 2011. [Abstract and Paper Link]

Computer2011
André DeHon and Benjamin Gojman. Crystals and Snowflakes: Building Computation from Nanowire Crossbars In IEEE Computer, Volume 44, Number 2, pp. 37--45, February, 2011. [Abstract and Paper Links]

RECOSOC2010
Nachiket Kapre and André DeHon. An NoC Traffic Compiler for efficient FPGA implementation of Parallel Graph Applications In Proceedings of the Workshop on Reconfigurable Communication-Centric Systems on Chip, May, 2010. [Abstract and Paper Links]

IETCDT2009
Benjamin Gojman, Harika Manem, Garret S. Rose, and André DeHon. Inversion Schemes for Sublithographic Programmable Logic Arrays In IET Computers and Digital Techniques, Volume 3, Number 6, Pages 525--642, November, 2009. [Abstract and IEEE link].

FPT2009a
Benjamin Gojman and André DeHon. VMATCH: Using Logical Variation to Counteract Physical Variation in Bottom-Up, Nanoscale Systems. In Proceedings of the IEEE International Conference on Field-Programmable Technology, pages 78--87, December, 2009. [Abstract and Paper Links]

FPT2009b
Nachiket Kapre and André DeHon. Parallelizing Sparse Matrix Solve for SPICE Circuit Simulation using FPGAs. In Proceedings of the IEEE International Conference on Field-Programmable Technology, pages 190--198, December, 2009. [Abstract and Paper Links]

FPL2009
Nachiket Kapre and André DeHon. Performance Comparison of Single-Precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core Processors. In Proceedings of the International Conference on Field Programmable Logic and Applications, pages 65--27, September, 2009. [Abstract and Paper Links]

FCCM2009
Nachiket Kapre and André DeHon. Accelerating SPICE Model-Evaluation using FPGAs. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, pages 37--44, April 2009. [Abstract and Paper Links]

TRVLSI2009
Helia Naeimi and André DeHon. Fault Secure Encoder and Decoder for NanoMemory Applications. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 17, Number 4, Pages 473--486, April 2009. [Abstract and IEEE link].

FPGA2009
Raphael Rubin and André DeHon. Choose-Your-Own-Adventure Routing: Lightweight Load-Time Defect Avoidance. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 23--32, February, 2009. [Abstract and Paper Link]

TC2009
Karl Papadantonakis, Nachiket Kapre, Stephanie Chan, and André DeHon. Pipelining Saturated Accumulation. In IEEE Transactions on Computers, Volume 58, Number 2, pp. 208--219, February, 2009. [Abstract and Paper Link]

NDCS2008
André DeHon. The Case for Reconfigurable Components with Logic Scrubbing: Regular Hygiene Keeps Logic FIT (low). In Proceedings of the IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems (NDCS2008), September 2008. [Abstract and Paper Links]

NANOTECHNOLOGY2008
Helia Naeimi and André DeHon. Fault-Tolerant Sub-lithographic Design with Rollback Recovery. In Nanotechnology, Volume 19, Number 11, Article 115708, March 19, 2008. [Abstract and Paper Links]

NANONETS2007
Helia Naeimi and André DeHon. Fault Tolerant Nano-Memory with Fault Secure Encoder and Decoder. In Proceedings of the International Conference on Nano-Networks (Nanonets2007), September 2007. [Abstract and Paper Links]

DFT2007
Helia Naeimi and André DeHon. Fault Secure Encoder and Decoder for Memory Applications. In Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS2007), September 2007. [Abstract and Paper Links]

ARITH2007
Nachiket Kapre and André DeHon. Optimistic Parallelization of Floating-Point Accumulation. In Proceedings of the IEEE Symposium on Computer Arithmetic (ARITH18), pp. 205--213, June 2007. [Abstract and Paper Links]

NANONETS2006b
Benjamin Gojman, Raphael Rubin, Concetta Pilotto, Tetsufumi Tanamoto, and André DeHon. 3D Nanowire-Based Programmable Logic. In Proceedings of the International Conference on Nano-Networks (Nanonets2006), September 2006. (best paper) [Abstract and Paper Links]

NANONETS2006a
Kumiko Numora, Keiko Abe, Shinobu Fujita, and André DeHon. Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices. In Proceedings of the International Conference on Nano-Networks (Nanonets2006), September 2006. [Abstract and Paper Links]

JETC2006
John E. Savage, Eric Rachlin, André DeHon, Charles M. Lieber, and Yue Wu. Radial Addressing of Nanowires. In ACM Journal on Emerging Technologies in Computing Systems, Volume 2, Number 2, Pages 129--154, April 2006. [Abstract and ACM Link].

JMM2006a
André DeHon, Yury Markovsky, Eylon Caspi, Michael Chu, Randy Huang, Stylianos Perissakis, Laura Pozzi, Joseph Yeh, and John Wawrzynek. Stream Computations Organized for Reconfigurable Execution. In Journal of Microprocessors and Microsystems, Volume 30, Number 6, Pages 334--354, September, 2006. [Abstract and DOI Link]

JMM2006b
André DeHon, Randy Huang, and John Wawrzynek. Stochastic Spatial Routing for Reconfigurable Networks. In Journal of Microprocessors and Microsystems, Volume 30, Number 6, Pages 301--318, September, 2006. [Abstract and DOI Link]

FCCM2006a
Michael deLorimier, Nachiket Kapre, Nikil Mehta, Dominic Rizzo, Ian Eslick, Raphael Rubin, Tomas Uribe, Thomas F. Knight, Jr. and André DeHon. GraphStep: A System Architecture for Sparse-Graph Algorithms. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, April 2006. [Abstract and Paper Links]

FCCM2006b
Nachiket Kapre, Nikil Mehta, Michael deLorimier, Raphael Rubin, Henry Barnor, Michael J. Wilson, Michael Wrighton, and André DeHon. Packet-Switched vs. Time-Multiplexed FPGA Overlay Networks. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, April 2006. (FCCM20) [Abstract and Paper Links]

ASPDAC2006
Michael Wrighton and André DeHon. SAT-Based Optimal Hypergraph Partitioning with Replication. In Proceedings of the Asia and South Pacific Design Automation Conference, January 2006. [Abstract and paper links].

ICFPT2005
Karl Papadantonakis, Nachiket Kapre, Stephanie Chan, and André DeHon. Pipelining Saturated Accumulation. In Proceedings of the International Conference on Field-Programmable Technology, December, 2005. [Abstract and paper links].

TNANO2005b
André DeHon. Deterministic Addressing of Nanoscale Devices Assembled at Sublithographic Pitches. In IEEE Transactions on Nanotechnology, Volume 4, Number 6, Pages 681--687, Nov. 2005. [Abstract and IEEE link].

JETC2005
André DeHon. Nanowire-Based Programmable Architectures. In ACM Journal on Emerging Technologies in Computing Systems, Volume 1, Number 2, Pages 109--162, July 2005. [Abstract and ACM Link].

IEEEDT2005
André DeHon and Helia Naeimi. Seven Strategies for Tolerating Highly Defective Fabrication. In IEEE Design and Test of Computers, Volume 22, Number 4, Pages 306--315, July-August 2005. [Abstract].

TNANO2005a
André DeHon, Seth Copen Goldstein, Philip J. Kuekes, and Patrick Lincoln. Non-Photolithographic Nanoscale Memory Density Prospects. In IEEE Transactions on Nanotechnology, Volume 4, Number 2, Pages 215--228, March 2005. [Abstract and IEEE link].

FPGA2005a
André DeHon. Design of Programmable Interconnect for Sublithographic Programmable Logic Arrays. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 127--137,February, 2005. [Abstract, paper, and slide links].

FPGA2005b
Michael deLorimier and André DeHon. Floating-Point Sparse Matrix-Vector Multiply for FPGAs. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 75--85, February, 2005. [Abstract, paper, and slide links].

ICFPT2004
Helia Naeimi and André DeHon. A Greedy Algorithm for Tolerating Defective Crosspoints in NanoPLA Design. In Proceedings of the International Conference on Field-Programmable Technology, pages 49--56, December, 2004. [Abstract and paper links].

TRVLSI2004a
André DeHon and Raphael Rubin. Design of FPGA Interconnect for Multilevel Metalization. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 12, Number 10, Pages 1038--1050, October 2004. [Abstract and IEEE link].

TRVLSI2004b
André DeHon. Unifying Mesh- and Tree-Based Programmable Interconnect In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 12, Number 10, Pages 1051--1065, October 2004. [Abstract and IEEE link].

LLNSD2004
André DeHon. Law of Large Numbers System Design. In Nano, Quantum and Molecular Computing: Implications to High Level Design and Validation, pp. 213--241, Kluwer, 2004. [Abstract].

FCCM2004
André DeHon, Joshua Adams, Michael DeLorimier, Nachiket Kapre, Yuki Matsuda, Helia Naeimi, Michael Vanier, and Michael Wrighton. Design Patterns for Reconfigurable Computing. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, April 2004. [Abstract and paper link].

FPGA2004
André DeHon and Michael J. Wilson. Nanowire-Based Sublithographic Programmable Logic Arrays. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 123--132, February, 2004. (FPGA20) [Abstract, paper, and slide links].

TNANO2003
André DeHon, Patrick Lincoln, and John E. Savage. Stochastic Assembly of Sublithographic Nanoscale Interfaces. In IEEE Transactions on Nanotechnology, Volume 2, Number 3, Pages 165--174, September 2003. [Abstract and IEEE link].

HOTCHIPS2003
André DeHon with Charles M. Lieber, Patrick Lincoln, and John E. Savage. Sub-lithographic Semiconductor Computing Systems. In Hot Chips Symposium 2003, August 17--19, 2003. [Abstract, paper, slides].

TNANO2003
André DeHon. Array-Based Architecture for FET-Based, Nanoscale Electronics. In IEEE Transactions on Nanotechnology, Volume 2, Number 1, Pages 23--32, Mar 2003. [Abstract and IEEE link].

FPGA2003a
Raphael Rubin and André DeHon. Design of FPGA Interconnect for Multilevel Metalization. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 154--163, February, 2003. [Abstract, paper, and slide links].

FPGA2003b
Michael Wrighton and André DeHon. Hardware-Assisted Simulated Annealing with Application for Fast FPGA Placement. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 33--42, February, 2003. [Abstract, paper, and slide links].

FPGA2003c
Randy Huang, John Wawrzynek, and André DeHon. Stochastic, Spatial Routing for Hypergraphs, Trees, and Meshes. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 78--87, February, 2003. [Abstract, paper, and slide links].

ICCAD2002
Michael Butts, André DeHon, and Seth Copen Goldstein, Molecular Electronics: Devices, Systems and Tools for Gigagate, Gigabit Chips. In Proceedings of the International Conference on Computer-Aided Design, pages 433--440, November, 2002. [Abstract, paper, and slide links].

UMC2002
André DeHon. Very Large Scale Spatial Computing. In Proceedings of the Third International Conference on Unconventional Models of Computation, pages 27--37, October 2002. [Abstract, paper, and slide links].

FCCM2002
André DeHon, Randy Huang, and John Wawrzynek. Hardware-Assisted Fast Routing. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, pages 205--215, April 2002. [Abstract, paper, and slide links].

NSC2002
André DeHon. Array-Based Architecture for Molecular Electronics. In Proceedings of the First Workshop on Non-Silicon Computation, February 2002. [Abstract, paper, and slide links].

SLIP2001
André DeHon. Rent's Rule Based Switching Requirements. In System-Level Interconnect Prediction (SLIP 2001), pages 197--204, March 31--April 1, 2001, [Abstract, paper links].

SPAA2000
André DeHon. Compact, Multilayer Layout for Butterfly Fat-Tree. In Twelfth Annual ACM Symposium on Parallel Algorithms and Architectures (SPAA 2000), pages 206--215, July 9-12, 2000. [Abstract, paper links].

Computer2000
André DeHon. The Density Advantage of Configurable Computing. IEEE Computer, 33(4):41--49, April 2000. [Abstract and paper link]

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Room# 315, 200 South 33rd Street, Electrical and Systems Engineering Department, Philadelphia, University of Pennsylvania, PA 19104.