Inversion Schemes for Sublithographic Programmable Logic Arrays
Benjamin Gojman,
Harika Manem, Garrett S. Rose
and André DeHon
IET Computers and Digital Techniques, Volume 3, Number 6, Pages 625--642, November, 2009.
A Programmable Logic Array (PLA) needs its inputs available in both the
positive and negative polarities. In lithographic-scale VLSI PLAs (and
PALs, PLDs) a buffer and inverter at the PLA input typically produce both
polarities from a single polarity input. However, the extreme regularity
required for sublithographic designs has driven nanoscale architectures
to consider alternate solutions.
Consequently, we compare three schemes: one based on producing both
polarities in a restoration stage (selective inversion), one based on a
local inversion stage, and one based on a full dual-rail logic
implementation. We develop a mapping flow for the dual-rail logic and
quantify its cost in both logical product terms and physical implementation
area. We develop area and timing models for all three schemes. Mapping
benchmarks from the Toronto 20 set, we are able to show that the local
inversion scheme is faster (less than one-fifth the latency), lower
energy (one-half the energy) and comparable size to the selective inversion scheme
and faster (less than half the latency), smaller (one-third of the
area), and lower energy (one-ninth the energy) than the dual-rail scheme.
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