Kung Fu Data Energy---Minimizing Communication Energy in FPGA Computations
Edin Kadric,
Kunal Mahajan, and André DeHon
Proceedings of the IEEE
Symposium on Field-Programmable Custom Computing Machines,
(FCCM, May 11--13, 2014)
The energy in FPGA computations can be dominated by data communication
energy, either in the form of memory references or data movement on
interconnect (e.g., over 75% of energy for single processor Gaussian
Mixture Modeling, Window Filtering, and FFT). In this paper, we explore
how to use data placement and parallelism to reduce communication energy.
We further introduce a new architecture for embedded memories, the
Continuous Hierarchy Memory (CHM), and show that it increases the
opportunities to reduce energy by strategic data placement. For three
common FPGA tasks in signal and image processing (Gaussian Mixture
Modeling, Window Filters, and FFTs), we show that data movement energy can
vary over a factor of 9.
The best solutions exploit parallelism and hierarchy
and are 1.8--6.0x more energy-efficient than designs that place all data in a
large memory bank. With the CHM, we can get an additional 10% improvement
for full voltage logic and 30--80% when operating the computation at
reduced voltage.
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