Reducing FPGA Compile Time with Separate Compilation for FPGA Building Blocks
Yuanlong Xiao, Dongjoon Park, Andrew Butt,
Hans Giesen, Zhaoyang Han,
Rui Ding, Nevo Magnezi, Raphael Rubin,
and André DeHon
Proceedings of the IEEE International Conference on Field-Programmable Technology,
(FPT, December 11--13, 2019)
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Today's FPGA compilation is slow because it compiles and co-optimizes the
entire design in one monolithic mapping flow. This achieves high quality
results but also means a long edit-compile-debug loop that slows
development and limits the scope of design-space exploration.
We introduce PRflow that
uses partial reconfiguration and an overlay packet-switched
network to separate the HLS-to-bitstream compilation problem for
individual components of the FPGA design. This separation allows both
incremental compilation, where a single component can be recompiled without
recompiling the entire design, and parallel compilation, where all the
components are compiled in parallel. Both uses reduce the compilation
time.
Mapping the Rosetta Benchmarks to a Xilinx XCZU9EG, we show compilation
times reduce from 42 minutes to 12 minutes (one case from 160 minutes to 18
minutes) when running on top of commercial tools from Xilinx. Using
Symbiflow (Project X-Ray/Yosys/VPR), we show preliminary evidence we can
further reduce most compile times under 5 minutes, with some components
mapping in less than 2 minutes.
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