VLIW-SCORE: Beyond C for Sequential Control of SPICE FPGA Acceleration
Nachiket Kapre and André DeHon
Proceedings of the IEEE International Conference on Field-Programmable Technology,
(FPT, December 12--14, 2011)
Many stand-alone, FPGA-based accelerators separate
the implementation of a computation into two components---(1) a large
parallel component that is realized as hardware on
spatial FPGA fabric and (2) a small control and co-ordination
component that is realized as software on embedded soft-core
processors like an off-the-shelf Xilinx Microblaze (or host offchip
CPU). While this hardware-software partitioning methodology
allows the designer to lower design effort when composing the
accelerator system, it introduces unnecessary Amdahl's Law
bottlenecks and limits scalability. In this paper, we show how
to avoid these limitations with VLIW-SCORE: a combination of
a high-level parallel programming framework called SCORE and
a custom, hybrid VLIW hardware organization. We demonstrate
the benefits of this methodology for the SPICE circuit simulator
when implementing the simulation control algorithms. With our
spatial mapping flow we are able to improve performance by
30% (mean across circuit benchmarks) when compared to
the Microblaze implementation for the Xilinx Virtex-6 LX760
FPGA. For complete application acceleration, we see an improved
speedup from 1.9x for the Microblaze-based design to 2.6x for
the hybrid, custom VLIW implementation when comparing a
Xilinx Virtex-6 LX760 FPGA (40nm) with an Intel Core i7 965
CPU (45nm).
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- [12/14/11] This paper received the Best Paper award for the conference.
N.b. See journal version for
composite SPICE implementation.
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