SPICE2: Spatial Processors Interconnected for Concurrent Execution for Accelerating the SPICE Circuit Simulator Using an FPGA
Nachiket Kapre and
André DeHon
IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems, Volume 31, Number 1,
pp. 9--12, DOI: 10.1109/TCAD.2011.2173199, January, 2012.
Spatial processing of sparse, irregular, double-precision floating-point
computation using a single field-programmable gate array (FPGA)
enables up to an order of magnitude speedup (mean 2.8x
speedup) over a conventional microprocessor for the SPICE circuit
simulator. We develop a parallel, FPGA-based, heterogeneous
architecture customized for accelerating the SPICE simulator to
deliver this speedup. To properly parallelize the complete
simulator, we decompose SPICE into its three constituent
phases---model evaluation, sparse matrix-solve, and iteration
control-and customize a spatial architecture for each phase
independently. Our heterogeneous FPGA organization mixes very large
instruction word, dataflow and streaming architectures into a
cohesive, unified design to match the parallel patterns exposed by
our programming framework. This FPGA architecture is able to
outperform conventional processors due to a combination of factors,
including high utilization of statically-scheduled resources,
low-overhead dataflow scheduling of fine-grained tasks, and
streaming, overlapped processing of the control algorithms. We
demonstrate that we can independently accelerate model evaluation
by a mean factor of 6.5x (1.4--23x) across a range
of nonlinear device models and matrix solve by
2.4x (0.6--13x) across various benchmark matrices
while delivering a mean combined speedup of
2.8x (0.2--11x) for the composite design when
comparing a Xilinx Virtex-6 LX760 (40 nm) with an Intel Core i7 965
(45 nm). We also estimate mean energy savings of 8.9x (up to
40.9x) when comparing a Xilinx Virtex-6 LX760 with an Intel
Core i7 965.
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