VMATCH: Using Logical Variation to Counteract Physical Variation in Bottom-Up, Nanoscale Systems
Benjamin Gojman and André DeHon
Proceedings of the IEEE International Conference on Field-Programmable Technology,
pp. 78--87 (FPT, December 09--11, 2009)
Nanowire building blocks provide a promising path
to small feature size and thus the ability to more densely
pack logic. However, the small feature size and novel, bottomup
manufacturing process will exhibit extreme variation and
produce many devices that operate outside acceptable operating
ranges. One-mapping-fits-all, prefabrication assignment of logical
functions to physical transistors that exhibit high threshold
variation will not work-combining the wide range of physical
variation in transistor threshold voltage with the wide range of
fanouts in the design produces an unworkably large composite
range of possible delays. Nonetheless, by carefully matching
the fanout of each net to the physical threshold voltages of
devices after fabrication, it is possible to reduce the net range of
path delays sufficiently to achieve high system yield. By adding
a modest amount of extra resources, we achieve 100% yield
for systems built out of devices with 38% variation, the ITRS
prediction for threshold variation in 5nm transistors. Moreover,
for these systems, we maintain delay, energy and area close to
the variation-free nominal case.
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Ben's master's
thesis includes expanded development of measurement techniques
and estimates the measurement precision necessary for the algorithm
to work.
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