We show that, with the VPR implementation of Pathfinder, perturbations of
initial conditions may cause critical paths to vary over ranges of 17--110%. We
further show that it is not uncommon
for VPR/Pathfinder to settle for solutions
that are >33% slower than necessary. These results suggest there is room
for additional innovation and improvement in FPGA routing. As one step in
this direction, we show how delay-targeted routing can reduce delay noise
to 13% for our worst-case design and below 1% for most designs. Anyone
who uses VPR as part of architecture or CAD research should be aware of
this noise phenomena and the techniques available to reduce its impact.
Copyright 2011 ACM,
Inc.
This is the author's version of the work. It is posted here by permission
of ACM for your personal use. Not for redistribution. The definitive
version was published in the Proceedings of the
International Symposium on Field-Programmable Gate Arrays,
(FPGA2011, February 27--March 1, 2011).
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