XBERT: Xilinx Logical-Level Bitstream Embedded RAM Transfusion
Matthew Hofmann,
Zhiyao Tang,
Jonathan Orgill,
Jonathan Nelson,
David Glanzman,
Brent Nelson,
and André DeHon
Proceedings of the IEEE
Symposium on Field-Programmable Custom Computing Machines,
(FCCM, May 9--12, 2021)
XBERT is an API and design toolset for zero-cost
access to the on-chip SRAM blocks on Xilinx architectures using the
device's configuration path. The XBERT API is high-level, allowing
developers to specify DMA-like data transfers of memory contents in terms
of the logical memories in the application source code and thus is
applicable to essentially any design targeting Xilinx devices. XBERT is
broadly accessible to application developers, hiding the low-level details
of physical mapping and bitstream encoding. XBERT is efficient,
consuming zero reconfigurable resources with no impact on Fmax. XBERT
achieves a bandwidth of 3--14 megabytes per second (MB/s) and
complete readback and translation of a memory in an isolated 36Kb block RAM
in less than 0.5 ms on a Xilinx UltraScale+ MPSoC Zynq.
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