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- Accurate Parallel Floating-Point Accumulator
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Bluespec System Verilog source release
for floating-point adder and accumulator designs described in the ARITH 2013 paper
Accurate Parallel Floating-Point Accumulation
- SAFE Processor
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Bluespec System Verilog source release for SAFE Processor
- dynamc Multi-Hash Cache (dMHC) Near Associative Memory
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Bluespec System Verilog source release
for dMHC designs described in the FPGA 2013 paper
Area-Efficient Near-Associative Memories on FPGAs
- Split-Merge Packet Switch NoC
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Bluespec System Verilog source release
for Split-Merge designs described in the FPT 2012 paper
FPGA
Optimized Packet-Switched NoC using Split and Merge Primitives
- Delay-Targeted VPR Patch
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VPR 5
patches and scripts for Delay-Targeted Routing described in the FPGA
2011 paper
Timing-Driven
Pathfinder Pathology and Remediation: Quantifying and Reducing Delay
Noise in VPR-Pathfinder
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