FPGA Optimized Packet-Switched NoC using Split and Merge Primitives
Yutian Huan and André DeHon
Proceedings of the IEEE International Conference on Field-Programmable Technology,
(FPT, December 10--12, 2012)
Due to their different cost structures, the architecture of switches for an
FPGA packet-switched Network-on-a-Chip (NoC) should differ from their ASIC
counterparts. The CONNECT network recently demonstrated several ways in
which packet-switched FPGA NoCs should differ from ASIC NoCs. However,
they also concluded that pipelining was not appropriate for the FPGA
switches. We show that the Split-Merge switch architecture is more
amenable to pipelining on FPGAs, achieving 300MHz
operation---up to three times the frequency and throughput of the CONNECT
switches---with only 13--37% more area. Furthermore, we show that the
Split-Merge switches are at least as efficient at routing traffic as the
CONNECT switches, meaning the 2--3x frequency translates directly into
two to three times the application performance.
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