Fast and Flexible FPGA Development using Hierarchical Partial Reconfiguration
Dongjoon Park,
Yuanlong Xiao,
and
André DeHon
Proceedings of the IEEE International Conference on Field-Programmable Technology,
(FPT, December 5--December 9, 2022)
To address slow FPGA compilation, researchers
have proposed to run separate compilations for smaller design
components in parallel. This approach provides small pages
on the FPGA, allowing users to separately generate partial
designs on the pages and load them together. However, this
method either forces users to manually decompose a design
into small components that fit in small, fixed-sized pages or to
use large, fixed-sized pages, reducing the potential compilation
speedup benefits. This restriction often results in suboptimal
decomposition of a design or diminishes productivity. To
overcome these limitations, we utilize the recently supported
Hierarchical Partial Reconfiguration technology from Xilinx to
generate a more flexible framework. Depending on the size
of user designs, our framework provides larger pages that
are hierarchically recombined from multiple smaller pages.
This flexibility relieves users of the burden to decompose the
original design and offers more opportunities for design-space
exploration. When tested on the ZCU102 embedded platform
with the Rosetta HLS benchmarks, our system achieves 1.4–4.9×
mapped application performance improvement compared to the
system with fixed-sized pages while still compiling in 2–5 minutes
(2.2–5.3× faster than the vendor tool).
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