Fault Secure Encoder and Decoder for Memory Applications
Helia Naeimi and André DeHon
Proceedings of the IEEE
International Symposium on
Defect and Fault Tolerance in VLSI Systems, (DFTS2007, Sept 26--28, 2007)
We introduce a reliable memory system that can
tolerate multiple transient errors in the memory words as well as
transient errors in the encoder and decoder (corrector) circuitry.
The key novel development is the fault-secure detector (FSD)
error-correcting code (ECC) definition and associated circuitry that
can detect errors in the received encoded vector despite
experiencing multiple transient faults in its circuitry. The
structure of the detector is general enough that it can be used for
any ECC that follows our FSD-ECC definition.
We prove that two known classes of Low-Density
Parity-Check Codes have the FSD-ECC property: Euclidean Geometry and
Projective Geometry codes. We identify a specific FSD-LDPC code that
can tolerate up to 33 errors in each memory word or supporting logic
that requires only 30% area overhead for memory blocks of 10 Kbits or larger.
Larger codes can achieve even higher reliability and lower area
overhead. We quantify the importance of protecting
encoder and decoder (corrector) circuitry and illustrate a scenario where the
system failure rate (FIT) is dominated by the failure rate of the encoder
and decoder.
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