Fault Secure Encoder and Decoder for NanoMemory Applications
Helia Naeimi and André DeHon
IEEE Transactions on Very Large Scale Integration (VLSI)
Systems , Volume 17, Number 4, Pages 473--486, April, 2009.
Memory cells have been protected from soft errors for more than a
decade; due to the increase in soft error rate in logic circuits,
the encoder and decoder circuitry around the memory blocks have
become susceptible to soft errors as well and must also be
protected. We introduce a new approach to design Fault-Secure
encoder and decoder circuitry for memory designs. The key novel
contribution of this paper is identifying and defining a new class
of Error-Correcting Codes whose redundancy makes the design of
Fault-Secure Detectors (FSD) particularly simple. We further
quantify the importance of protecting encoder and decoder circuitry
against transient errors, illustrating a scenario where the system
failure rate (FIT) is dominated by the failure rate of the encoder
and decoder. We prove that Euclidean Geometry Low-Density
Parity-Check (EG-LDPC) codes have the Fault-Secure Detector
capability. Using some of the smaller EG-LDPC codes we can tolerate
bit or nanowire defect rates of 10% and fault rates of
10-18 upsets/device/cycle, achieving a FIT rate at or below one
for the entire memory system and a memory density of
1011 bits/cm2 with nanowire pitch of 10nm for memory
blocks of 10Mbits or larger. Larger EG-LDPC codes can achieve even
higher reliability and lower area overhead.
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