PLD: Fast FPGA Compilation to Make Reconfigurable Acceleration Compatible with Modern Incremental Refinement Software Development
Yuanlong Xiao, Eric Micallef, Andrew Butt, Matthew Hofmann, Marc Alston, Matthew Goldsmith, Andrew Merczynski-Hait and
André DeHon
Proceedings of the International Conference on Architectural
Support for Programming Languages and Operating Systems,
pp. 933--945, (March 1--3, 2022)
FPGA-based accelerators are demonstrating significant absolute performance
and energy efficiency compared with general-purpose CPUs. While FPGA
computations can now be described in standard, programming languages, like
C, development for FPGAs accelerators remains tedious and inaccessible to
modern software engineers. Slow compiles (potentially taking tens of hours)
inhibit the rapid, incremental refinement of designs that is the hallmark
of modern software engineering. To address this issue, we introduce
separate compilation and linkage into the FPGA design flow, providing
faster design turns more familiar to software development. To realize this
flow, we provide abstractions, compiler options, and compiler flow that
allow the same C source code to be compiled to processor cores in seconds
and to FPGA regions in minutes, providing the missing -O0 and -O1 options
familiar in software development. This raises the FPGA programming level
and standardizes the programming experience, bringing FPGA-based
accelerators into a more familiar software platform ecosystem for software
engineers.
© 2022 held by authors; Creative Commons
Attribution-NonCommercial-NoDerivates 4.0 International License.
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