Performance Comparison of Single-Precision SPICE
Model-Evaluation on FPGA, GPU, Cell, and multi-core Processors
Nachiket Kapre and André DeHon
Proceedings of the International Conference on Field Programmable Logic and Applications,
pp. 65--72 (FPL, August 31--September 2, 2009)
Automated code generation and performance tuning techniques for concurrent
architectures such as GPUs, Cell and FPGAs can provide integer factor speedups
over multi-core processor organizations for data-parallel, floating-point
computation in SPICE Model-Evaluation. Our Verilog AMS compiler produces code
for parallel evaluation of non-linear circuit models suitable for use in SPICE
simulations where the same model is evaluated several times for all the devices
in the circuit. Our compiler uses architecture specific parallelization
strategies (OpenMP for multi-core, PThreads for Cell, CUDA for GPU, statically
scheduled VLIW for FPGA) when producing code for these different architectures.
We automatically explore different implementation configurations (e.g. unroll
factor, vector length) using our
performance-tuner to identify the best possible configuration for each
architecture. We demonstrate speedups of 3--182x
for a Xilinx Virtex5 LX 330T, 1.3--33x for an IBM Cell, and
3--131x for an NVIDIA 9600 GT GPU over a 3 GHz Intel Xeon 5160
implementation for a variety of single-precision device models.
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N.b. See journal version for
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