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Implementation of Computation Group


Exploiting Partially Defective LUTs: Why You Don't Need Perfect Fabrication

André DeHon and Nikil Mehta
Proceedings of the IEEE International Conference on Field-Programmable Technology, (FPT, December 9--11, 2013)

Shrinking integrated circuit feature sizes lead to increased variation and higher defect rates. Prior work has shown how to tolerate the failure of entire LUTs and how to tolerate failures and high variation in interconnect. We show how to use LUTs even when they are partially defective---a form of fine-grained defect tolerance. We characterize the defect tolerance of a range of mapping strategies for defective LUTs, including LUT swapping in a cluster, input permutation, input polarity selection, defect-aware packing, and defect-aware placement. By tolerating partially defective LUTs, we show that, even without allocating dedicated spare LUTs, it is possible to achieve near perfect yield with cluster local remapping when roughly 1% of the LUT multiplexers fail to switch. With full, defect-aware placement, this can increase to 10--25% with just a few extra rows and columns. In contrast, substitution of perfect LUTs to dedicated spares only tolerates failure rates of 0.01--0.05%.

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  • [12/10/13] This paper received the Outstanding Paper Award for the conference.

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