How should we perform component-specific adaptation for FPGAs? Prior
work has demonstrated that the negative effects of variation can be
largely mitigated using complete knowledge of device characteristics and
full per-FPGA CAD flow. However, the
cost of per-FPGA characterization and mapping could be prohibitively
expensive. We explore light-weight options for per-FPGA mapping that
avoid the need for a priori device characterization and perform
less expensive per FPGA customization work. We characterize the tradeoff
between Quality-of-Results (energy, delay) and per-device mapping costs
for 7 design points ranging from complete mapping based on
knowledge to no per-device mapping. We show that it is possible to get
48--77% of the component-specific mapping delay benefit
or 57% of the energy benefit with a mapping that
takes less than 20 seconds per FPGA. An incremental solution can start execution after a
21ms bitstream load and converge to 77% delay benefit after
18 seconds of runtime.
Copyright
Giesen, Rubin, Gojman, DeHon 2017. Publication rights licensed to ACM.
This is the author's version of the work. It is posted here for your
personal use.
Not for redistribution. The definitive version was published in the Proceedings of the
International Symposium on Field-Programmable Gate Arrays,
http://dx.doi.org/10.1145/3020078.3026124.
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