ExHiPR: Extended High-level Partial Reconfiguration for Fast Incremental FPGA Compilation
Yuanlong Xiao,
Dongjoon Park,
Zeyu Jason Niu, Aditya Hota,
and André DeHon
ACM Transactions on Reconfigurable Technology and Systems (TRETS), September, 2023
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Partial Reconfiguration (PR) is a key technique in the application design on modern FPGAs. However, current PR tools
heavily rely on the developer to manually conduct PR module definition, floorplanning, and flow control at a low level. The
existing PR tools do not consider High-Level-Synthesis languages either, which are of great interest to software developers.
We propose HiPR, an open-source framework, to bridge the gap between HLS and PR. HiPR allows the developer to define
partially reconfigurable C/C++ functions, instead of Verilog modules, to accelerate the FPGA incremental compilation and
automate the flow from C/C++ to bitstreams. We use a lightweight Simulated Annealing floorplanner and show that it can
produce high-quality PR floorplans an order of magnitude faster than analytic methods. By mapping Rosetta HLS benchmarks,
we demonstrate that the incremental compilation can be accelerated by 3-10x compared with state-of-the-art Xilinx Vitis
flow without performance loss, at the cost of 15-67% one-time overlay set-up time.
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