Case for Fast FPGA Compilation Using Partial Reconfiguration
Dongjoon Park, Yuanlong Xiao, Nevo Magnezi, and André DeHon
Proceedings of the International Conference on Field Programmable Logic and Applications,
(FPL, August 27--31, 2018)
Despite the FPGA's advantages over other hardware
platforms, long compilation time prevents FPGA engineers from
efficiently exploring the design space and discourages new users
who want to quickly iterate for debugging. To reduce compilation
time, this work adopts a divide-and-conquer approach using Partial Reconfiguration
with a Packet-Switched Fat-Tree network.
Partially reconfigured leaves in the packet-switched network are
independent from each other and can be compiled separately
in parallel. Also, when a minor fix is required to a bitstream,
only the corresponding leaves need to be incrementally compiled.
Preliminary experimental evidence from our work-in-progress
effort illustrates how a 30 minute full-chip compile time can be
reduced to 7 minutes.
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