When are FPGAs more energy efficient than processors? This question is
complicated by technology factors and the wide range of application
characteristics that can be exploited to minimize energy. Using a
wire-dominated energy model to estimate the absolute energy required for
programmable computations, we determine when spatially organized
programmable computations (FPGAs) require less energy than temporally
organized programmable computations (processors). The point of crossover
will depend on the metal layers available, the locality, the SIMD wordwidth
regularity, and the compactness of the instructions. When the Rent
Exponent, p, is less than 0.7, the spatial design is always more energy
efficient. When p=0.8, the technology offers 8-metal layers for routing,
and data can be organized into 16b words and processed in tight loops of no
more than 128 instructions, the temporal design uses less energy when the
number of LUTs is greater than 64K. We further show that heterogeneous
multicontext architectures can use even less energy than the p=0.8, 16b
word temporal case.
Copyright
DeHon 2014. Publication rights licensed to ACM.
This is the author's version of the work. It is posted here for your
personal use.
Not for redistribution. The definitive version was published in the Proceedings of the
International Symposium on Field-Programmable Gate Arrays,
http://dx.doi.org/10.1145/2554688.2554781.
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