Recent work shows how to use on-chip structures to measure the fabricated
delays of fine-grained resources on modern FPGAs. We show that
simultaneous measurement of multiple, disjoint paths will result in
different measured delays from isolated configurations that measure a
single path. On the Cyclone III, we show differences as large as +/-33ps
on 2ns-long paths, even if the simultaneously configured logic is not
active. This is over 20x the measurement precision used on these devices
and over 50% of the observed delay spread in prior work. We characterize
the magnitude of the impact of simultaneous measurements and identify
strategies and cases that can reduce the difference. Furthermore, we
provide a potential explanation for our observations in terms of
self-heating and the configurable clock network architecture. These
experiments point to phenomena that must be characterized to better
formulate on-chip FPGA delay measurements and to properly interpret their
results.
Copyright
Linscott, Gojman, Rubin, DeHon 2016. Publication rights licensed to ACM.
This is the author's version of the work. It is posted here for your
personal use.
Not for redistribution. The definitive version was published in the Proceedings of the
International Symposium on Field-Programmable Gate Arrays,
http://dx.doi.org/10.1145/2847263.2847334.
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