Timing Extraction identifies the delay of fine-grained components within an
FPGA. From these computed delays, the delay of any path can be
calculated. Moreover, a comparison of the fine-grained delays allows a
detailed understanding of the amount and type of process variation that
exists in the FPGA. To obtain these delays, Timing Extraction measures,
using only resources already available in the FPGA, the delay of a small
subset of the total paths in the FPGA. We apply Timing Extraction to the
Logic Array Block (LAB) on an Altera Cyclone III FPGA to obtain a view of
the delay down to near individual LUT granularity, characterizing
components with delays on the order of a few hundred picoseconds with a
resolution of +/-3.2 ps. This information reveals that the 65nm process
used has, on average, random variation of σ/μ=4.0% with components
having an average maximum spread of 83ps. Timing Extraction also shows
that as VDD decreases from 1.2V to 0.9V in a Cyclone IV 60nm FPGA, paths
slow down and variation increases from σ/μ=4.3% to σ/μ=5.8%, a
clear indication that lowering VDD magnifies the impact of random
variation.
Copyright 2013 ACM,
Inc.
This is the author's version of the work. It is posted here by permission
of ACM for your personal use. Not for redistribution. The definitive
version was published in the Proceedings of the
International Symposium on Field-Programmable Gate Arrays,
(FPGA2013, February 11--13 2013).
N.B. An expanded, journal
version appears in TRETs.
A later paper addressesing interconnect appears in FCCM.
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