GROK-LAB: Generating Real On-chip Knowledge for Intra-cluster Delays using Timing Extraction
Benjamin Gojman,
Sirisha Nalmela, Nikil
Mehta, Nicholas Howarth, and André DeHon
ACM Transactions on Reconfigurable Technology and Systems (TRETS) ,
Volume 7, Number 4, DOI: 10.1145/2597889, December, 2014.
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Timing Extraction identifies the delay of fine-grained components within an
FPGA. From these computed delays, the delay of any path can be
calculated. Moreover, a comparison of the fine-grained delays allows a
detailed understanding of the amount and type of process variation that
exists in the FPGA. To obtain these delays, Timing Extraction measures,
using only resources already available in the FPGA, the delay of a small
subset of the total paths in the FPGA. We apply Timing Extraction to the
Logic Array Block (LAB) on an Altera Cyclone III FPGA to obtain a view of
the delay down to near individual LUT SRAM cell granularity, characterizing
components with delays on the order of tens to a few hundred picoseconds
with a resolution of +/-3.2 ps, matching the expected error bounds. This
information reveals that the 65nm process used has, on average, random
variation of σ/μ=4.0% with components having an average maximum
spread of 83ps. Timing Extraction also shows that as VDD decreases from
1.2V to 0.9V in a Cyclone IV 60nm FPGA, paths slow down and variation
increases from σ/μ=4.3% to σ/μ=5.8%, a clear indication
that lowering VDD$ magnifies the impact of random variation.
Copyright Gojman et al. 2014. This is the author's version of the work. It is posted
here for your personal use. Not for redistribution. The definitive
version was published in ACM Transactions on Reconfigurable Technology and Systems (TRETS),
http://dx.doi.org/10.1145/2597889
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