Parallelizing Sparse Matrix Solve for SPICE Circuit Simulation using FPGAs
Nachiket Kapre and André DeHon
Proceedings of the IEEE International Conference on Field-Programmable Technology,
pp. 190--198 (FPT, December 09--11, 2009)
Fine-grained dataflow processing of sparse Matrix-Solve computation
(Ax=b) in the SPICE circuit simulator can provide an order of
magnitude performance improvement on modern FPGAs. Matrix Solve is the dominant
component of the simulator especially for large circuits and is invoked
repeatedly during the simulation, once for every iteration. We process
sparse-matrix computation generated from the SPICE-oriented KLU solver in
dataflow fashion across multiple spatial floating-point operators coupled to
high-bandwidth on-chip memories and interconnected by a low-latency network.
Using this approach, we are able to show speedups of 1.2-64x (geometric
mean of 8.8x) for a range of circuits and benchmark matrices when
comparing double-precision implementations on a 250MHz Xilinx Virtex-5 FPGA
(65nm) and an Intel Core i7 965 processor (45nm).
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N.b. See journal version for
composite SPICE implementation.
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