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Fault Tolerant Nano-Memory with Fault Secure Encoder and Decoder

Helia Naeimi and André DeHon
Proceedings of the International Conference on Nano-Networks, (Nanonets2007, Sept 24--26, 2007)

We introduce a nanowire-based, sublithographic memory architecture tolerant to transient faults. Both the storage elements and the supporting ECC encoder and corrector are implemented in dense, but potentially unreliable, nanowire-based technology. This compactness is made possible by a recently introduced Fault-Secure detector design [ref]. Using Euclidean Geometry error-correcting codes (ECC), we identify particular codes which correct up to 8 errors in data words, achieving a FIT rate at or below one for the entire memory system for bit and nanowire transient failure rates as high as 10-17 upsets/device/cycle with a total area below 1.7x the area of the unprotected memory for memories as small as 0.1 Gbit. We explore scrubbing designs and show the overhead for serial error correction and periodic data scrubbing can be below 0.02% for fault rates as high as 10-20 upsets/device/cycle. We also present a design to unify the error-correction coding and circuitry used for permanent defect and transient fault tolerance.

Copyright 2007 ACM, Inc.

N.b. See expanded journal version.
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