FPGAs have the advantage that a single component can be
configured post-fabrication to implement almost any computation.
However, designing a one-size-fits-all memory architecture
causes an inherent mismatch between the needs of the application
and the memory sizes and placement on the architecture.
Nonetheless, we show that an energy-balanced design for
FPGA memory architecture (memory block size(s),
memory banking, and spacing between memory banks) can guarantee that the
energy is always within a factor of 2 of the optimally-matched
architecture. On a combination of the VTR 7 benchmarks and
a set of tunable benchmarks, we show that
an architecture with internally-banked 8Kb and 256Kb memory
blocks has a 31% worst-case energy overhead (8% geomean).
In contrast, monolithic 16Kb memories (comparable to 18Kb and 20Kb memories
used in commercial FPGAs) have a 147% worst-case energy overhead
(24% geomean).Furthermore, on benchmarks
where we can tune the parallelism in the implementation to improve energy
(FFT, Matrix-Multiply, GMM, Sort, Window Filter), we show that we can
reduce the energy overhead by another 13% (25% for the geomean).
Copyright
Kadric, Lakata, DeHon 2015. Publication rights licensed to ACM.
This is the author's version of the work. It is posted here for your
personal use.
Not for redistribution. The definitive version was published in the Proceedings of the
International Symposium on Field-Programmable Gate Arrays,
http://dx.doi.org/10.1145/2684746.2689062.
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