Pipelining Saturated Accumulation
Karl Papadantonakis,
Nachiket Kapre,
Stephanie Chan, and André DeHon
IEEE Transactions on Computer, Volume 58, Number 2,
pp. 208--219, February, 2009.
Aggressive pipelining and spatial parallelism allow integrated circuits
(e.g., custom VLSI, ASICs,
FPGAs) to achieve high throughput on many Digital Signal Processing
applications. However, cyclic data dependencies in the computation can
limit parallelism and reduce the efficiency and speed of an implementation.
Saturated accumulation is an important example where such a cycle limits
the throughput of signal processing applications. We show how to
reformulate saturated addition as an associative operation so that we can
use a parallel-prefix calculation to perform saturated accumulation at any
data rate supported by the device. This allows us, for example, to design
a 16-bit saturated accumulator which can operate at 280MHz on a Xilinx
Spartan-3 (XC3S-5000-4) FPGA, the maximum frequency supported by the
component's DCM.
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