Penn Logo
Vertical Line

Implementation of Computation Group


Self-Adaptive Timing Repair

Hans Giesen, Raphael Rubin, Benjamin Gojman, and André DeHon published in IEEE Design and Test, Volume 34, Number 6, pp. 54--62, November-December, 2017.

Transistor parameters in today's small feature technologies vary widely among transistors due to process effects, over time due to aging, and across environment and usage due to temperature. Margining for worst-case parameters results in excessive delay and energy for all chips. By measuring resource characteristics on chip and adapting resource usage, we can reduce delay and energy margins. Using modern SoC FPGAs, we introduce a lightweight approach to measure delay during operation in order to identify and repair slow links throughout the lifetime of the component.


Room# 315, 200 South 33rd Street, Electrical and Systems Engineering Department, Philadelphia , University of Pennsylvania, PA 19104.