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Implementation of Computation Group


Choose-Your-Own-Adventure Routing: Lightweight Load-Time Defect Avoidance

Raphael Rubin and André DeHon
Proceedings of the International Symposium on Field-Programmable Gate Arrays, pp. 23--32, (FPGA2009, February 22--24, 2009)

Aggressive scaling increases the number of devices we can integrate per square millimeter but makes it increasingly difficult to guarantee that each device fabricated has the intended operational characteristics. Without careful mitigation, component yield rates will fall, potentially negating the economic benefits of scaling. The fine-grained reconfigurability inherent in FPGAs is a powerful tool that can allow us to drop the stringent requirement that every device be fabricated perfectly in order for a component to be useful. To exploit inherent FPGA reconfigurability while avoiding full CAD mapping, we propose lightweight techniques compatible with the current single bitstream model that can avoid defective devices, reducing yield loss at high defect rates. In particular, by embedding testing operations and alternative path configurations into the bitstream, each FPGA can avoid defects by making only simple, greedy decisions at bitstream load time. With 20% additional tracks above the minimum routable channel width, routes can tolerate 0.01% switch defect rates, raising yield from essentially 0% to near 100%.

Copyright 2009 ACM, Inc. This is the author's version of the work. It is posted here by permission of ACM for your personal use. Not for redistribution. The definitive version was published in the Proceedings of the International Symposium on Field-Programmable Gate Arrays, (FPGA2009, February 22--24, 2009).

N.b. See expanded journal version.

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