GROK-INT: Generating Real On-chip Knowledge for Interconnect Delays Using Timing Extraction
Benjamin Gojman
and André DeHon
Proceedings of the IEEE
Symposium on Field-Programmable Custom Computing Machines,
(FCCM, May 11--13, 2014)
With continued scaling, all transistors are no longer created equal. The delay of a length 4 horizontal routing
segment at coordinates (23,17) will differ from one at (12,14) in the same FPGA and from the same segment in another
FPGA. The vendor tools give conservative values for these delays, but knowing exactly what these delays are can be
invaluable. In this paper, we show how to obtain this information, inexpensively, using only components that already
exist on the FPGA (configurable PLLs, registers, logic, and interconnect). The techniques we present are general and
can be used to measure the delays of any resource on any FPGA with these components. We provide general algorithms for
identifying the set of useful delay components, the set of measurements necessary to compute these delay components, and
the calculations necessary to perform the computation. We demonstrate our techniques on the interconnect for an Altera
Cyclone-III (65nm). As a result, we are able to quantify over a 100ps spread in delays for nominally identical
routing segments on a single FPGA.
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