|
 |
|
|
Fast FPGA Compilation
FPGA compilation is notoriously slow, typically measured in hours with 10s of hours common for large datacenter FPGAs. This results in a slow edit-compile-debug loop that discourages software programmers from adopting FPGAs and limits design-space exploration.
In this project, we explore ways to accelerate FPGA compilation to get the edit-compile-debug loop down to the range of minutes or even seconds.
Examples from our recent work include:
- REFINE: Runtime Execution Feedback for INcremental Evolution on FPGA Designs
- ExHiPR: Extended High-level Partial Reconfiguration for Fast Incremental FPGA Compilation
- Fast and Flexible FPGA Development using Hierarchical Partial Reconfiguration
- HiPR: High-level Partial Reconfiguration for Fast Incremental FPGA Compilation
- PLD: Fast FPGA Compilation to Make Reconfigurable Acceleration Compatible with Modern Incremental Refinement Software Development
- Fast Linking of Separately-Compiled FPGA Blocks without a NoC
- Reducing FPGA Compile Time with Separate Compilation for FPGA Building Blocks
- Case for Fast FPGA Compilation Using Partial Reconfiguration
|
||||||||||||||||||