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Please check out IC group git repo for the recent projects.
- PowerOpt
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source release for
power optimized memory mapping described in FPGA 2015 paper
Impact of Memory Architecture on FPGA Energy Consumption
- Low-Fat Pointers
-
Bluespec System Verilog source release
for Fat Pointer designs described in the CCS 2013 paper
Low-Fat Pointers: Compact Encoding and Efficient Gate-Level Implementation
of Fat Pointers for Spatial Safety and Capability-based Security
- Accurate Parallel Floating-Point Accumulator
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Bluespec System Verilog source release
for floating-point adder and accumulator designs described in the ARITH 2013 paper
Accurate Parallel Floating-Point Accumulation
- SAFE Processor
-
Bluespec System Verilog source release for SAFE Processor
- dynamc Multi-Hash Cache (dMHC) Near Associative Memory
-
Bluespec System Verilog source release
for dMHC designs described in the FPGA 2013 paper
Area-Efficient Near-Associative Memories on FPGAs
- Split-Merge Packet Switch NoC
-
Bluespec System Verilog source release
for Split-Merge designs described in the FPT 2012 paper
FPGA
Optimized Packet-Switched NoC using Split and Merge Primitives
- Delay-Targeted VPR Patch
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VPR 5
patches and scripts for Delay-Targeted Routing described in the FPGA
2011 paper
Timing-Driven
Pathfinder Pathology and Remediation: Quantifying and Reducing Delay
Noise in VPR-Pathfinder
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